1. Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter
Project Lead The Way, Inc.
Copyright 2009

2. Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter
This presentation will
Define asynchronous counters.
Define the terms states and modulus.
Provide multiple examples of asynchronous counters designed with D & J/K flip-flops.
Explain an asynchronous counter’s ripple effect.
Summarize the asynchronous counter design steps.
Project Lead The Way, Inc.
Copyright 2009

3. Asynchronous Counters
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counters
Only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
Asynchronous counters are slower than synchronous counters (discussed later) because of the delay in the transmission of the pulses from flip-flop to flip-flop.
Asynchronous counters are also called ripple counters because of the way the clock pulses, or ripples, its way through the flip-flops.
Project Lead The Way, Inc.
Copyright 2009

4. States / Modulus / Flip-Flops
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
States / Modulus / Flip-Flops
The number of flip-flops determines the count limit or number of states:
States = 2 (# of flip-flops)
The number of states used is called the MODULUS.
For example, a Modulus-12 counter (Mod-12) would count from 0 (0000) to 11 (1011) and would require four flip-flops (24 = 16 states; 12 are used)
Project Lead The Way, Inc.
Copyright 2009

5. Asynchronous Counter D-Flip Flop – 1 Bit
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter D-Flip Flop – 1 Bit Q0 1
Repeats →
CLK
Project Lead The Way, Inc.
Copyright 2009

6. Asynchronous Counter Up Counter – D-Flip Flops – 2 Bit
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Up Counter – D-Flip Flops – 2 Bit
Note: Since we want Q1 to toggle on the falling edge of Q0, we must clock the second flip-flop from the of the first.
“0”
“1”
“2”
“3” Q1 1 1
Repeats → Q0 1 1
CLK
Project Lead The Way, Inc.
Copyright 2009

7. Asynchronous Counter Up Counter – D-Flip Flops – 3 Bit
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Up Counter – D-Flip Flops – 3 Bit
Note: The CLKs are connected to the of the previous flip-flop.
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7” Q2 1 1 1 1 1 1 1 Q1
Repeats → Q0
CLK
Project Lead The Way, Inc.
Copyright 2009

8. Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
The Ripple Effect
As the clock input “ripples” from the first flip-flop to the last, the propagation delays from the flip-flops accumulate. This causes the Q outputs to change at different times, resulting in the counter briefly producing incorrect counts. For example, as a 3 bit ripple counter counts from 7 to 0, it will briefly output the count 6 and 4. 7 1 6 1 4 1 Q2 1 Q1 Q0
CLK
1 mSec
100 nSec
Project Lead The Way, Inc.
Copyright 2009

9. Asynchronous Counter Down Counter – D-Flip Flops – 3 Bit
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Down Counter – D-Flip Flops – 3 Bit
Note: The CLKs are connected to the Q of the previous flip-flop.
“7”
“6”
“5”
“4”
“3”
“2”
“1”
“0” Q2 1 1 1 1 1 1 1 Q1
Repeats → Q0
CLK
Project Lead The Way, Inc.
Copyright 2009

10. Asynchronous Counter Summary
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Summary
Up Counters
Connect the CLK input to the Q output with the opposite polarity
Down Counters
Connect the CLK input to the Q output with the same polarity
Project Lead The Way, Inc.
Copyright 2009

11. Asynchronous Counter Up Counter – JK-Flip Flops – 3 Bit
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Up Counter – JK-Flip Flops – 3 Bit
Note: The active low CLKs are connected to the Q of the previous flip-flop.
“0”
“1”
“2”
“3”
“4”
“5”
“6”
“7” Q2 1 1 1 1 1 1 1 Q1
Repeats → Q0
CLK
Project Lead The Way, Inc.
Copyright 2009

12. Asynchronous Counter Down Counter – JK-Flip Flops – 3 Bit
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Down Counter – JK-Flip Flops – 3 Bit
Note: The active low CLKs are connected to the
of the previous flip-flop.
“7”
“6”
“5”
“4”
“3”
“2”
“1”
“0” Q2 1 1 1 1 1 1 1 Q1
Repeats → Q0
CLK
Project Lead The Way, Inc.
Copyright 2009

13. Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Modulus Asynchronous Counter Up Counter – D Flip Flops – 3 Bit / Mod-6 (0-5)
Note: The upper limit of the count is 5; therefore, the reset circuit must detect a 6 (count +1).
“0”
“1”
“2”
“3”
“4”
“5”
“0”
“1” Q2 1 1 1 1 1 1 Q1
Repeats → Q0
RESET
Project Lead The Way, Inc.
Copyright 2009

14. Asynchronous Counter Design Steps
Asynchronous Counters with SSI Gates
Digital Electronics TM
3.2 Asynchronous Counters
Asynchronous Counter Design Steps
Select Counter Type
Up or Down
Modules
Select Flip-Flop Type
D (74LS74)
J/K (74LS76)
Determine Number of Flip-Flops
2 # Flip-Flops  Modules
Design Count Limit Logic
Input to reset logic circuit is count limit plus one for up counters (minus one for down counters)
Project Lead The Way, Inc.
Copyright 2009