1. Electronics Technology
Digital Electronics
Electronics Technology
Sachin Sharma
Counters

2. ASYNCHRONOUS COUNTERS
Only LSB flip-flop controlled by the clock input
Also known as a RIPPLE COUNTER
Two or more “T” flip-flops interconnected, output
of each flip-flop connected to clock input of the next.
Modulus- number of stable states in each flip-flop cycle
Modulus = N= number of flip-flops
Highest number in count =

3. BUILD A 4 BIT RIPPLE COUNTER
1. 4 JK flip-flops in toggle mode- all JK inputs tied high
2. Q outputs connected to clock input of following flip-flop
3. FF A = LSB (one with clock input); toggles when input clock
toggles from high to low; FF D = MSB
4. FF B, C, D do not toggle till receive NGT from proceeding FF
5. Direction of count can be reversed by complementing each FF’s output or complementing each FF’s input

4. TEST
1. What is the term for the number of counts in one counter cycle?
Modulus of the counter
2. How is the modulus determined?
3. Since only the first flip-flop of a ripple counter is controlled by a clock,
the counter is ____________________?
Asynchronous
4. What is the mod number of a counter containing 5 flip-flops? 32
5. What is the highest count of a four bit counter? 31

5. PROGRAMMING A RIPPLE COUNTER
Counters may be made to recycle after any desired count by using a gate to reset the counter.
CONVERT MOD 8 TO MOD6
UNSTABLE STATE

6. HOW TO BUILD A COUNTER TO GO FROM ZERO TO MOD NUMBER X
1. Determine smallest number of FF’s such that
2. Connect a NAND gate output to asynchronous clears of all FF’s
3. Determine which FF’s will be high at count = X
Connect the Q outputs of these FF’s to NAND gate inputs

7. BUILD A COUNTER THAT COUNTS FROM ZERO TO NINE (X=MOD 10)
1. Determine smallest number of FF’s such that
thus 4 FF’s are required
2. Connect a NAND gate to asynchronous clears of all FF’s
3. Determine which FF’s will be high at count = X
Connect the Q outputs of these FF’s to NAND gate inputs 1

8. PROGRAMMING COUNTERS USING JK INPUTS
Counters can be controlled using the JK inputs
Low on JK of 1st FF will cause it to stop toggling on any count
High or low at JK inputs forces counter to skip states

9. ASYNCHRONOUS DOWN COUNTER
Direction of count can be reversed by
(a) complementing each FF’s output or
(b) complementing each FF’s input

10. COUNTER PROBLEM
1. What is the value of the last usable state before the NAND gate resets the circuitry?
2. What value does the NAND gate reset the value to?
3. What is the modulus of this counter?
4. If count starts at decimal 11 and receives seven clock pulses, what is the new value on the counter?
5. What is the unstable state of the counter?

11. COUNTER PROBLEM
1. What is the value of the unstable state, in decimal?
2. At what value does the NAND gate set the counter to?
3. If QA=1, QB=1, and QC=0, and 5 clock pulses are applied:
QC= QB= QA=
4. What is the modulus of this counter?

12. BCD COUNTER
Binary counter that counts from 0000 to 1001 before it recycles (MOD-10).
Widespread applications where pulses or events are to be counted and the results displayed on a decimal numerical read-out.
Also used for dividing a pulse frequency exactly by 10.
Cascading BCD counters to count and display from 000 to 999.

13. Two 7493s can be combined to produce a MOD-60 Counter

14. DIGITAL CLOCK

15. COUNTERS
ASYNCHRONOUS
SYNCHRONOUS

16. SYNCHRONOUS COUNTERS Two or more FF’s connected as “T” FF’s.
All FF’s in the counter are clocked at the same time.
Advantage over the ripple counter is speed and accuracy but more complex.

17. SYNCHRONOUS COUNTERS MOD <2
A NAND control gate is used to clear the counter before the full count.

18. SYNCHRONOUS COUNTERS
UP/DOWN

19. COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial Counter): each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain.
Synchronous Counter (a.k.a. Parallel Counter): all the FF’s in the counter are clocked at the same time.
Up Counter: counter counts from zero to a maximum count.
Down Counter: counter counts from a maximum count down to zero.
BCD Counter: counter counts from 0000 to 1001 before it recycles.
Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously
Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF.
Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF.

20. RING COUNTER
Shift register counter with feedback from Q of last FF back to first FF input

21. JOHNSON COUNTER
Shift register in which the inverted output of the last FF is fed back to the input of the first FF.

22. A PROGRAMMABLE COUNTER
Lab 18.
A PROGRAMMABLE COUNTER
Design a four-bit counter controlled by two control lines X and Y that behaves according to the truth table.

23. A PROGRAMMABLE COUNTER
Lab 18.
A PROGRAMMABLE COUNTER

24. RIPPLE COUNTER
Binary Output
Clock Input
Pulse 5
Pulse 6
Pulse 8
Pulse 4
Pulse 7
Pulse 1
Pulse 3
Pulse 2
This 4-bit counter has 16 states and
will count from binary 0000 through 1111
and then reset back to 0000.
The counter has a modulus of 16.
On the next clock pulse (8) all FFs
will toggle because each will receive
a H-to-L pulse- one after another.
Watch the count ripple thru the counter.
PS and CLR input
are
INACTIVE
All J-K flip-flops
in the
TOGGLE MODE

25. RIPPLE COUNTER WITH WAVEFORMS
Binary Output
Clock Input
Pulse 5
Pulse 4
Pulse 2
Pulse 3
Pulse 1
Clock input
1s output
2s output
4s output
FFs triggered on
H-to-L pulse.
CLK toggles 1s FF.
1s FF toggles 2s FF.
2s FF toggles 4s FF.

26. DECADE COUNTER All J & K inputs = 1 All PR inputs = 1 0 0 0 1 0 0 0 0
Initial count at 0111
Binary Output
Clock Input
Pulse 8
Pulse 2
Pulse 1
Pulse 4
Pulse 3
Pulse 7
Pulse 6
Pulse 5
To clear input
of each FF
Short negative pulse
All J & K inputs = 1
All PR inputs = 1
Count is at 1001.
Next clock pulse will increment counter for a
short time to 1010 which will activate the NAND gate
and reset the counter to 0000.
To change mod-16 counter to decade counter:
Reset count to 0000 after 1001 (9) count.
When count hits 1010 reset to 0000.
See added 2-input NAND gate that clears all
JK FFs to 0 when count hits 1010.

27. DOWN COUNTER
Initial count
set at
binary 111
0 1 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
Pulse 2
Pulse 5
Pulse 4
Pulse 1
Pulse 3
Changes from Ripple Up Counter are
wiring from Q’ outputs (instead of Q outputs)
to the CLK input of the next FF.

28. SELF-STOPPING DOWN COUNTER
Watch count on
Pulse 8.
The count remained
at binary 000.
0 1 1
0 1 0
0 0 0
1 0 1
0 0 1
1 0 0
1 1 0
1 1 1
Pulse 8
Pulse 1
Pulse 7
Pulse 2
Pulse 6
Pulse 5
Pulse 4
Pulse 3
This is a 3-bit down counter.
The 1s FF is in TOGGLE mode when counting (J & K = 1).
The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate
when the count decrements to The count stops at 000.

29. COUNTER USED FOR FREQUENCY DIVISION
 4
200 Hz
 8
400 Hz
100 Hz
50 Hz
 2
 16
Clock Input
800 Hz

30. USING THE 7493 COUNTER IC Counters are available in IC form.
Either ripple (7493 IC) or synchronous (74192 IC) counters are available.
? Hz
400 Hz
100 Hz
? Hz
? Hz
800 Hz
1600 Hz
7493 Counter IC
wired as a 4-bit
binary counter

31. MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B).
74HC85
Magnitude
Comparator
A = B
A < B
A > B
A(0)
A(1)
A(2)
A(3)
B(0)
B(1)
B(2)
B(3)
Input binary 0111
Input binary 1111
Input binary 0001
HIGH
HIGH
Input binary 0110
Input binary 0111
Input binary 1100
HIGH

32. TROUBLESHOOTING EQUIPMENT
Logic Probe
Logic Pulser
Logic Clip (logic monitor)
Digital IC Tester
DMM/Logic Probe
DMM or VOM
Dual-trace Oscilloscope
Logic Analyzer

33. SIMPLE TROUBLESHOOTING HINTS
Feel top of IC to determine if it is hot
Look for broken connections, signs of excessive heat
Smell for overheating
Check power source
Trace path of logic through circuit
Know the normal operation of the circuit