Achieving Signal and Timing Requirements for a DDR2 Based System

Achieving Signal and Timing Requirements for a DDR2 Based System
Kim Owen, Bruce Caryl Application Engineers Mentor Graphics

DDR2 Presentation Overview
DDR2 Technology Review Planning DDR2 Topology and Entering Constraints Review Routing Guidelines Verifying SI and Timing Margins Using the Hyperlynx 8.0 DDR/2/3 Wizard BC-KO, U2U, Nov 2008

DDR2 Overview What is DDR2, anyway?
DDR2 = “Double-Data-Rate v2” synchronous DRAM memory Physically, it’s a source-synchronous technology Small groups of data (or “byte lanes”) have their own “private” clocks or strobes Each 8-bit lane gets its own strobe BC-KO, U2U, Nov 2008

DDR2 Overview Data bandwidth is doubled by clocking data on every edge of the strobe (rising and falling) DDR2 is popular, because it’s cheap and fast: JEDEC spec supports 400, 533, 667, 800, and 1066 Mbps x64 bits  GBps ©2003 Micron Technology, Inc. All rights reserved. BC-KO, U2U, Nov 2008

New for DDR2 Technology DDR2 Operating Speeds
DDR2-400 (200 MHz clock) DDR2-533 (266 MHz clock) DDR2-667 (333 MHz clock) DDR2-800 (400 MHz clock) Source-Synchronous interface like original DDR Recommended board impedance is 50 ohms DQS DQ0 DQ1 DQ2 DQS DQ0 DQ1 DQ2 Strobe Data Strobe Data Like the first version of DDR, DDR2 offers multiple operating speeds. DDR2 starts out at DDR2-400 which would have a 200 MHz clock and goes up to DDR800. If you have the option, it’s better to implement a DDR 400 interface as opposed to a DDR2-400 interface. DDR2 has more latency so you’d get better performance with DDR Improvements in bandwidth do occur once you go to DDR533 BC-KO, U2U, Nov 2008

Technical Background DDR2 timing margins are so tight, signal-integrity and timing calculations are critical @ 800 Mbps rate, the bit period is only 1.25 ns This means previous bits linger on the copper bus even while later bits are being sent An effect called “intersymbol interference” (ISI) Each bit’s shape and timing depends previous bits Bits are interfering with each other  ISI, and therefore the shape of each bit is different  different timing There is no longer a single delay: Every bit delay varies at least a little on every clock cycle! BC-KO, U2U, Nov 2008

New for DDR2 Electrical Characteristics
Vih ac Vref Vil ac Vih dc Vil dc DDR2 uses SSTL18 buffer technology 1.8V technology Class I drivers for point to point connection – Half drive strength Class II drivers for multi-drop connection – Full drive strength Some new voltages to remember Vref = 900 mV Used for setting up switching thresholds (Vih and Vil) Vih/Vil AC Thresholds = Vref +/- 250 mV for DDR2-400 & 533 = Vref +/- 200 mV for DDR2-667 & 800 Vih/Vil DC Thresholds =Vref +/- 125 mV for all DDR2 Let’s talk a little about the DDR buffer technology. DDR uses SSTL-II technology for the I/O which operates on a 2.5V rail. The bus is bi-directional so you need to make sure signals are clean on both Read and Write operations. The recommended impedance of a DDR interface varies depending on the loading conditions and which driver class you are using. A low impedance can cause signal slew rates above 4.5V/ns which exceeds the value allowed by the DDR spec. Too high of an impedance will slow the edge rate down too much and you will not meet your setup/hold time requirements. It’s best to simulate your specific design with different impedance values to determine the best solution. BC-KO, U2U, Nov 2008

DDR2 Signaling – Example SSTL-1.8
NEW: VDDQ (1.8V nominal) VOH(MIN) VIH 1.025V 0.9V AC 1.150V VIH DC Note from PowerPoint Expert: colors have been changed. 0.775V VI L DC VIL 0.650V AC Receiver VOL (MAX) VSSQ Transmitter

NEW: DDR2 On Die Termination
ODT – On Die Termination Built into the controller IC and DDR2 SDRAM Selectable resistor values 50 Ohm, 75 Ohm, 150 Ohm ODT turns on / off depending on Read or Write operation An important feature of DDR2 was the implementation of ODT or On Die Termination. ODT removes the need to have external series terminations as well as the pull-up terminations on the data/strobe lines on your board. It’s important to note that pull-ups termination for the Address/Control signals are still necessary. Also, there are still series terminations on the DIMM. ODT improves signal integrity on the bus by adjusting the termination value through the ODT control signal. It offers values of 50 ohms, 75 ohms, and 150 ohms depending on whether you’re performing a read or a write operation and the loading condition on the bus. We’ll get into more detail about how this works on the next slide. * Courtesy of Micron BC-KO, U2U, Nov 2008

BC-KO, U2U, Nov 2008

New: On Die Termination BC-KO, U2U, Nov 2008

ODT Values must be chosen and specified for Simulation

NEW: DDR2 Delay Measurement
Slew Rate affects switching time Charge Model Simplification: The area under the curve affects when the buffer switches + Dt - Dt Vih AC 2 V/ns 1 V/ns Let’s talk a little about the DDR buffer technology. DDR uses SSTL-II technology for the I/O which operates on a 2.5V rail. The bus is bi-directional so you need to make sure signals are clean on both Read and Write operations. The recommended impedance of a DDR interface varies depending on the loading conditions and which driver class you are using. A low impedance can cause signal slew rates above 4.5V/ns which exceeds the value allowed by the DDR spec. Too high of an impedance will slow the edge rate down too much and you will not meet your setup/hold time requirements. It’s best to simulate your specific design with different impedance values to determine the best solution. 0.5 V/ns Vref BC-KO, U2U, Nov 2008

Setup Nominal Slew Rate
New Measurement Requirement

Setup Tangent Line Slew Rate
New Measurement Requirement

Clock Derating Table Derating can consume 50% of your Interconnect Timing Budget! tIS (total setup time) = tIS (base) + ΔtIS (derating) tIH (total hold time) = tIH (base) + ΔtIH (derating)

533 MBS DDR2 Write Timing Budget
Pre-Route planning and constraint management is essential BC-KO, U2U, Nov 2008

DDR2 Planning and Constraints

DDR2 Design Guidelines What results are important
We need to constrain 4 critical lengths Net length from the controller to the 1st DIMM slot Net length between DIMM slots Net length from last slot to the pull-up term. (only Address/Command) All DQS/DQ groups should be length matched to minimize skew within the group and across the channel VDD VTT #1 #2 #3 Memory Controller DIMM Slot 1 VTT Pull-up Resistors DIMM Slot 2 BC-KO, U2U, Nov 2008

#2 The length between the DIMMs is typically around 425 mils #1 This length from the controller to the first DIMM is typically between 1.9” and 4.5” VDD VDD #1 #2 Memory Controller DIMM Slot 1 DIMM Slot DIMM Slot BC-KO, U2U, Nov 2008

#3 The length from the last DIMM to the pull-up resistors is typically 200 mils to 550 mils Only applies to the Address/Command/Control nets – Data nets use ODT No timing importance here VDD VTT #3 VTT Pull-up Resistors DIMM Slot BC-KO, U2U, Nov 2008

#4 This constraint is very critical. A data group (DQ) has an associated strobe (DQS); This group should be length matched to each other with minimum skew Typical constraints are about 50 mils within the group Try to spread this out across the channel +/- 30 mils for length #1 +/- 20 mils for length #2 Overall skew between byte lanes should be +/- 500 mils Skew between address nets should be +/- 200 mils VDD VTT Memory Controller DIMM Slot 1 VTT Pull-up Resistors DIMM Slot 2 BC-KO, U2U, Nov 2008

DDR2 Design Guidelines Spacing Recommendations
Varies depending on stackup Typically rules of thumb say 3H spacing For a 5 mil dielectric this would be 15 mils For signals coupled closely to reference planes, often 1.5H can be used or ~8 mils BC-KO, U2U, Nov 2008

Mentor DDR2 Design Kit Design kits for DDR2 are available online through SupportNet Design kits include presentations and example LineSim schematics with typical DDR2 memory board topology BC-KO, U2U, Nov 2008

Key Signal Groups Address/Command (A, BA, RAS#, CAS#, WE#)
Single ended, parallel, terminated to VTT (0.9V), registered on rising edge of clock May use 2T timing if too heavily loaded Control (S#, CKE, ODT) Each bank has own control signal (less loading) Must use 1T timing Clocks Differential , terminated on die with ODT Data Single ended, bi-directional, synchronized to Data Strobes, terminated on die with ODT Data Strobes Differential, bi-directional, terminated on die with ODT Can be single ended but differential more commonly used One diff pair for each byte lane BC-KO, U2U, Nov 2008

DIMM Layout Address/Command (A0) Data (DQ0) BC-KO, U2U, Nov 2008

DIMM Layout Clock (CK0) Data Strobe (DQS8) BC-KO, U2U, Nov 2008

Power Supplies Three power supplies are required
VDD 1.8 V Supply for I/O Drivers (SSTL1.8) and DRAM core Controller core may have additional requirements VREF 0.9 volt switching reference voltage used by DRAMs and controller Critical value since all switching is referenced to VREF Isolate and/or shield with ground VTT 0.9 volt termination supply (1/2 VDD) Use wide island trace area +/- 2% AC noise VTT = VREF +/- 40 mV VREF and VTT should be properly decoupled VREF is more sensitive to noise, so it cannot share the VTT plane BC-KO, U2U, Nov 2008

Constraint Entry System (CES)
Use CES to fully constrain all important aspects of a net Trace width, impedance, layer, clearance, min/max delay, matching, diff pair rules, etc. Constrain one net in bus, create a constraint template, apply template to all other nets in bus Constraints are used by Auto Router and manual routing Constraints can be entered from schematic or layout (synchronized during forward and back annotation) Allows engineering to create verifiable requirements Ensures implementation matches requirements BC-KO, U2U, Nov 2008

Address/Command/Control Signals
Single ended, parallel bus architecture Synchronized to memory clock Switch on positive edge of clock Terminated to VTT (0.9V) Address/Command Can have heavy capacitive loading (36 DRAMS in 2 DIMM configuration) Control signals have separate signal for each bank (1/4 the load in 2 DIMM configuration) For DDR2-667 (333 MHz clock), Address changes at 167 MHz max (1T Timing) BC-KO, U2U, Nov 2008

Address Topology Simplified
Model trace lengths, widths, layers, termination, timing Create constraints for layout Use intended board stackup Length of trace to terminator Length of trace between connectors Stackup DIMM modeled as EBD (Electrical Board Desc.) Length of trace on PCB BC-KO, U2U, Nov 2008

Address Simulation (1T Timing)
36 DRAM loads Waveforms at 4 DRAMS Marginal signal quality Limited timing budget BC-KO, U2U, Nov 2008

Improving Address/Command Quality and Timing
Provide a separate (duplicate) signal driver for each DIMM at the controller Use 2T timing to allow two clock cycles per address change Add a compensation capacitor for each signal (18-27pF recommended) Only recommended for > 18 memory chip loads BC-KO, U2U, Nov 2008

Address Simulation (2T Timing)
36 DRAM loads Waveforms at 6 DRAMS Improved signal quality Ample timing budget BC-KO, U2U, Nov 2008

Address Constraints Controller to first DIMM max = 3200 th
First DIMM to second DIMM max = 650 th Second DIMM to terminator max = 600 th All Address lines matched to 200 th All Address lines matched to CK_N0 to 5mm (200 th) Prevents clock-to-address skew Sometimes implemented as average of clock lengths BC-KO, U2U, Nov 2008

Address Constraints in CES

Command/Control Constraints in CES

Clock Signals Differential Signals On die termination (ODT) is used
AC compensation cap recommended for DIMMs Three clock pairs per DIMM when using unbuffered DIMMs BC-KO, U2U, Nov 2008

Clock Topology Breakout Length of trace on PCB Connector DIMM

Clock Topology with Vias and AC Compensation
RAM Model Model via transitions Model of compensation cap Provide complete constraint data Lengths Route layers Via types BC-KO, U2U, Nov 2008

Clock Topology without AC Compensation
Waveform at all receivers No compensation cap Multiple transitions on rcv6 Poor overall signal quality BC-KO, U2U, Nov 2008

Clock Topology with AC Compensation
Waveform at all receivers 10pF compensation cap Good signal quality Clean transitions BC-KO, U2U, Nov 2008

Clock Constraints Controller to DIMM max = 3900 th
DIMM to AC compensation max = 600 th Clock diff pair match = 25 th “Clock Differential Pairs” Net Class Inner Layer Routing (layers 3, 5) Often specified to be routed on same layer 4 mil trace width with 4 mil spacing Coupling may vary based on stackup 100 ohm differential impedance BC-KO, U2U, Nov 2008

Clock Constraints in CES

Data (DQ) Signals Single ended nets On die termination (ODT) is used
Must be matched tightly to data strobes (DQS) Must be matched between byte lanes (8 bit groups) For write operation: DIMM receiving data is set to 150 ohm ODT DIMM not receiving data is set to 75 ohm ODT For read operation Controller is set to 150 ohm ODT DIMM supplying data is set to open DIMM not supplying data is set to 75 ohm ODT BC-KO, U2U, Nov 2008

Data (DQ) Topology DIMMs BC-KO, U2U, Nov 2008

Data (DQ) Simulation Waveform DIMM1 front, write
DIMMS set to 150 ohm ODT No eye opening BC-KO, U2U, Nov 2008

Data (DQ) Simulation Waveform DIMM1 front, write
DIMM2 set to 75 ohm ODT DIMM1 set to 150 ohm ODT 680 ps eye opening, 3% jitter BC-KO, U2U, Nov 2008

Data (DQ) Constraints Controller to DIMM max = 3900 th
DIMM X1 to DIMM X2 max = 650 th Match to all other DQ signals in byte lane Tolerance = 100 th Match to corresponding DQS “DQ Data” Net Class Can be layer restricted Due to matching with DQS, DQ is also matched to CK_N0 +/- 25 mm (1 inch) Results in Byte Lanes matching to 1 inch BC-KO, U2U, Nov 2008

Data (DQ) Constraints in CES

Data Strobe (DQS) Signals
Differential signals On die termination (ODT) is used Must be matched tightly to associated data group Data is clocked in on both edges Must be matched between byte lanes (8 bit groups) Must be matched to Clocks within +/- 25 mm BC-KO, U2U, Nov 2008

Data Strobe DQS Topology
DIMM DIMM Connectors BC-KO, U2U, Nov 2008

Data Strobe (DQS) Simulation
Controller, DIMM1 and DIMM2 BC-KO, U2U, Nov 2008

Data Strobe DQS Topology Simplified DIMM Interface
Simple topology for creating initial constraints Specify impedance, trace width, spacing, layer, length BC-KO, U2U, Nov 2008

Data Strobe (DQS) Constraints
Controller to DIMM max = 3940 th DIMM X1 to DIMM X2 max = 650 th Match to all DQ signals in corresponding Byte Lane Tolerance = 100 th “DQS Differential Pairs” Net Class Layer restricted to 3 and 5 4 mil trace width with 4 mil spacing Due to matching with DQ, DQS is also matched to CK_N0 +/- 25 mm (1 inch) Results in Byte Lanes matching to 1 inch BC-KO, U2U, Nov 2008

Data Strobe (DQS) Constraints in CES

Routing Guidelines BC-KO, U2U, Nov 2008

DDR2 Routing Auto Route methodology BC-KO, U2U, Nov 2008

Tuned Clock Route Example
Routed board using Auto Route methodology BC-KO, U2U, Nov 2008

Some Routing Guidelines
Place critical delays on pin pairs, since “trace length” in CES is actually the sum of all copper on net Pin pairs will include pin package lengths (set in CES), and series elements Typically constrain both sides of series element separately Add virtual pins using Netline Manipulation in Expedition, or Virtual Pins in CES Pin pairs can be defined from virtual pins to components Useful for specifying stub length from trace to component or for balanced topologies Perform pin swapping within byte groups to improve routing If Memory Controller is an FPGA, I/O Designer can improve route-ability by improving pin position Auto-route by classes, one class at a time BC-KO, U2U, Nov 2008

More Routing Guidelines
Freescale recommended route order 1. Route data 2. Route address/command 3. Route control 4. Route clocks 5. Route power Route each data group (8 bits of DQ, DQS, DM) on the same layer Keep data groups away from control and address signals to minimize crosstalk Route all signals over reference planes Route longest trace first in matched groups Isolate and protect VREF from noise Manufactures provide more details… BC-KO, U2U, Nov 2008

Post Route Analysis for SI and Timing

Tips for DDR2 setup: Perform usual BoardSim setup
Seven Habits for Highly Successful HyperLynx Perform DDR Wizard setup Interactively probe one net of each type data, addr, clk, dqs, cntrl Find and fix Model problems Set up problems Signal Quality problems BC-KO, U2U, Nov 2008

Clocks at Receiver Die, Slow

Address Lines, Fast BC-KO, U2U, Nov 2008

Address Lines, Slow BC-KO, U2U, Nov 2008

Address Lines, Slow, Full Strength

DQ0 Write @ Receiver, Fast and Slow

DQ0 Read @ Receiver, Fast and Slow

DQS Write to Slot 1, Fast BC-KO, U2U, Nov 2008

DQS Read from Slot 1, Fast BC-KO, U2U, Nov 2008

Analyzing DDR2 Timing BC-KO, U2U, Nov 2008

DDR2: The Bad News for SI Simulation
Thorough DDR2 SI measurement is nearly impossible to do manually! Input buffer hysteresis complicates SI measurements Programmable ODT and Buffers Create dozens of new simulation cases Logic switching times change with waveshape Requires time consuming, manual measurements BC-KO, U2U, Nov 2008

DDR2: The Bad News for Timing Closure
DDR2 timing measurements are much more complex than previous timing measurements Source-synchronous technology requires measurement of multiple nets, not individual nets Data + strobes, addr/comm/ctrl + clocks, strobes+clocks ISI requires setup and hold times to be measured on multiple clock edges And on every strobe edge (rising and falling) for data Set up and Hold times must be adjusted for slew rates that differ from a nominal 1 V/ns BC-KO, U2U, Nov 2008

DDR2 Timing Budget (Write)

Example Timing Budget for DDR2 RDIMM
Register clock to output is determined from the Simulation Helps in getting more accurate timing budget BC-KO, U2U, Nov 2008

DDR2 Timing Considerations
Setup slew rate measurement Rising Edge Last crossing of Vref + DC Guard-band to first crossing of Vih-ac Falling Edge Last crossing of Vref – DC Guard-band to first crossing of Vil-ac Hold slew rate measurement First crossing of Vil-dc to the first crossing of Vref – AC Guard-band First crossing of Vih-dc to the first crossing of Vref + AC Guard-band Vih ac Vih dc Vref + Guard-band Vref Vref – Guard-band Vil dc Vil ac Let’s talk a little about the DDR buffer technology. DDR uses SSTL-II technology for the I/O which operates on a 2.5V rail. The bus is bi-directional so you need to make sure signals are clean on both Read and Write operations. The recommended impedance of a DDR interface varies depending on the loading conditions and which driver class you are using. A low impedance can cause signal slew rates above 4.5V/ns which exceeds the value allowed by the DDR spec. Too high of an impedance will slow the edge rate down too much and you will not meet your setup/hold time requirements. It’s best to simulate your specific design with different impedance values to determine the best solution. BC-KO, U2U, Nov 2008

DDR2 Timing Characteristics
Setup If any of the signal falls to the right of the nominal slew rate in the switching region, signal must be derated Hold If any of the signal falls to the left of the nominal slew rate in the switching region, signal must be derated Let’s talk a little about the DDR buffer technology. DDR uses SSTL-II technology for the I/O which operates on a 2.5V rail. The bus is bi-directional so you need to make sure signals are clean on both Read and Write operations. The recommended impedance of a DDR interface varies depending on the loading conditions and which driver class you are using. A low impedance can cause signal slew rates above 4.5V/ns which exceeds the value allowed by the DDR spec. Too high of an impedance will slow the edge rate down too much and you will not meet your setup/hold time requirements. It’s best to simulate your specific design with different impedance values to determine the best solution. BC-KO, U2U, Nov 2008

DDR2: The Good News for Simulation
Hyperlynx 8.0 DDR/2/3 Wizard Automatically Determines DDR2 SI and Timing Margins Performs Multi-Cycle source-synchronous timing measurements Drives batch simulations with PRBS stimulus over all corners Automatically performs Write/Read ODT (on-die-termination) settings Automatically computes DDR2 slew de-rating Exhaustive Timing Margin calculations Automatic report generation in Excel BC-KO, U2U, Nov 2008

DDR2: The Good News for Simulation… HyperLynx v8.0 DDR/2/3 Wizard
DDR Wizard is based on a Set-Up Checklist: Includes a left-side contents list Easy to jump to only a few specified pages… …and provides built-in “context” visibility BC-KO, U2U, Nov 2008

Assign Memory Controller and Data Rate

Specify Memory Assignments

Assign IBIS Models BC-KO, U2U, Nov 2008

Automatic/Manual DDR Net Assignment
Auto mapping based on signal names in assigned IBIS Models BC-KO, U2U, Nov 2008

Specify ODT Model Configuration

Specify ODT Buffer Activation

Assign Timing Models Standard Timing Models Provided

Viewing DDR2 Timing Models

Select Stimulus and Crosstalk

Choose Simulation Options

Choose Run and Report Options

Tips for DDR2 setup: Run a batch audit and simulation with a few nets of each type data, addr, clk, dqs, cntrl Audit will quickly locate these problems: Missing IBIS-model assignments Broken signal paths Due to missing resistor-pack models, etc. Correct reference-designator mappings For example, DRAMs called “REGx…”  resistor Incorrect DIMM HYP file used Main board clock connecting to a DIMM address line, etc. BC-KO, U2U, Nov 2008

Automatic Simulation Pre-Check
For most errors, double-clicking will jump to the wizard page BC-KO, U2U, Nov 2008

Tips for DDR2 setup: Watch for problems in IBIS models
The Wizard is good, but not all powerful DDR2 strobes can be single-ended or differential; some IBIS models force manual editing to make this selection In the [Diff_Pin] section Some x8 DRAMs allow the data mask bit to be used instead as an extra strobe (“RDQS”) during read operations May require more manual changes in the IBIS file Model Selector Additional IBIS thresholds BC-KO, U2U, Nov 2008

DDR2 Wizard Output Reports
DDR2 output reports / files: DDR2 Batch Engine Comprehensive output reporting! - including clearly formatted Excel spreadsheets .XLS report .XLS report .CSV waveform (optional) All files go into a sub-directory below the HYP dir, with a time-stamped name - like “DDR_Results_Aug _18h-32m” .LOG file Details about every operation in the run; reports any problems encountered Optionally, every single waveform created during simulation; sufficient for reproducing all timing measurements manually BC-KO, U2U, Nov 2008

Comprehensive DDR2 Timing Margin Report
Descriptive column headings - including timing formulae Detailed timing measurements Failures marked in red BC-KO, U2U, Nov 2008

DDR2 Signal Integrity Results
Signal distortion at receiver BC-KO, U2U, Nov 2008

DDR2 Setup Timing Margin Report

DDR2 Hold Timing Margin Report

Summary BC-KO, U2U, Nov 2008

Summary DDR2 presents significant new technical challenges to designers Planning and defining constraints is critical to achieving a successfully routed board Simulate pre-route to validate constraints Exhaustive post-route analysis ensures that timing requirements are met Mentor board products can help achieve reliable DDR2 designs BC-KO, U2U, Nov 2008

Credits and Acknowledgements
DDR1/DDR2 Memory Systems Design (AN138), Steve Foster, Freescale Semiconductor, 2006 DDR2 and DDR3 Challenges, Randy Wolff, Micron Technology, 2008 DDR2 Technology Workshop, Steve McKinney & Pat Carrier, Mentor Graphics, 2006 HyperLynx v8.0 DDR2 Simulation, Steve Kaufer, Mentor Graphics, 2008 JESD8-15A, JEDEC Solid State Technology Assn, 2003 Slew Rate De-rating in IBIS, Randy Wolff, Micron Technology, 2008 TN DDR2 Design Guide for Two-DIMM Systems, Micron Technology, 2004 BC-KO, U2U, Nov 2008

Achieving Signal and Timing Requirements for a DDR2 Based System

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Achieving Signal and Timing Requirements for a DDR2 Based System

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