1. Electromigration Analysis for MTTF Calculations
Mahesh N. Jagadeesan
Analog IC Research Group
The University of Texas, Arlington

2. Electromigration Current induced transport of the conducting material
Electromigration is caused by high current density stress
Major source of breakdown in electronic devices
Electromigration and Joule Heating (JH)
Peak current density is calculated with the help of layout parameters
Peak current density solutions used to generate adequately safe current density design guidelines

3. Electromigration estimation
Electromigration Analysis
– Checks for violations of the current density limits
MTTF Calculation
- Assess the mean-time-to-failure (MTTF) for all wire segments

4. Electromigration Analysis
Computation of peak current densities for power, ground and other metal lines in a circuit
Extraction of RC parameters from layout designed, using circuit netlist
Verification of the estimated peak values with the values extracted from the layout parameters

5. Computation of peak current densities
Jpeak comprehends simultaneously both of the relevant temperature dependent mechanisms-electromigration (EM) and joule heating (JH)
Parametric dependence of Jpeak on lead width, underlying oxide thickness, and EM current density are given

6. Joule Heating effect on current densities
For JH, the steady state equation for quasi one dimensional (1-D) heat transport equation is given by
where
Tm - mean metal lead temperature
Tref - maximum allowed junction reference temperature (100 C)
Kox - underlying oxide thermal conductivity
tox - underlying oxide thickness
tm - metal thickness
wm - metal width
ρm - temperature dependent metal resistivity.

7. Computation of peak current densities
Figure shows three single level metal systems
From Hunter et al, “Self -consistent solutions for allowed interconnect current density”
1-D solutions are considered the worst-case “thermally-wide” case
Quasi-two-dimensional (2-D) solution as found analytically by Bilotti et al, for weff accurate to 3%
weff = wm tox

8. EM lifetime on current density
Black’s equation for dependence of EM lifetime on current density and temperature ;
where
JEM - dc current density at temperature Tm
Em - activation energy for the EM mechanism JEM, dc, ref - dc EM current density specification at the temperature Tref.

9. Peak Current density
For a unipolar (and rectangular) pulsed dc waveform with duty cycle r and peak current density Jpeak, the standard definition of Jrms results
Reason for unipolar pulsed dc is that, maximum allowed Jpeak for a symmetrical pure ac is greater than for the pulsed dc case, making the latter a worst-case
Where

10. Values of material parameters used
Parameter Values used
Values of material parameters used
Parameter
Value
Units
Kox
1.52
W .m-1 .K-1 Km
243
ρm (Tm)
E -8
Ω .m Em
0.7
e.V
Jem, dc, ref
6 E 9
A .m-2
Tox
3 E –6 .m Tm
0.5 E –6 Wm kB
1.38 E –23
J / k

11. Extraction of interconnect Area from layout
Interconnect with an insufficient width may be subject to electromigration
Crucial to address the problems of current densities and electromigration during layout generation
Capacitance of each net has two components:
- area and perimeter

12. Capacitance Extraction for Area estimation
There are three capacitance components at any node
Overlap capacitance (Cover)
Lateral capacitance (Clat)
Fringing capacitance (Cfr)
From Arora et al, “Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits”

13. Cint = (Carea W+2.Clength).L
Area from Capacitance
Intrinsic capacitance two components:
- overlap and fringing capacitances
overlap capacitance
Where Carea is capacitance per unit area (fF/µm2), and W.L is the area (..m2).
fringing capacitance
Intrinsic capacitance is the sum of these two components
Cover = Carea W. L
Cfr=2.Clength.L
Cint = (Carea W+2.Clength).L

14. Interconnect Area Extraction
Modelling approach is not restricted to the structure
Structures such as vias are not modelled using this approach
Overlap capacitance is observed using Spectre simulator from Cadence tools
Capacitance per unit area, Carea is estimated using the Advanced Design Systems (ADS)

15. Interconnect width extraction
Two different ways researched
From parasitic capacitances,
- using metal interconnect area
- width calculated with some assumptions for a constant length
Metal width from Virtuoso Custom Router (VCR)
- from the design rules file as documented by the VCR when creating a route between devices in a circuit

16. From parasitic capacitances
For overlap capacitance, Cover
- Schematic and layout created
- DRC, LVS checks performed
- extraction with DIVA RCX cadence tool
For Carea from the Advanced Design systems (ADS)
- microstrip line is considered with unit values for width and length
- S-parameters generated
- SPICE model generator creates R and C values for unit area
WxL obtained using the expressions shown before

17. Schematic of a comparator circuit
Schematic of a comparator circuit from Virtuoso Schematic viewer

18. Layout of the comparator circuit
Layout of the comparator circuit, from Virtuoso XL, layout editor

19. Layout with parasitics
Layout with parasitics extracted using the DIVA tool for RCX

20. Extracted netlist with capacitance values

21. Microstrip line for capacitance estimation
Microstrip line for capacitance per area estimation in ADS

22. S-parameters generated
S-parameters generated for the microstrip line in ADS

23. SPICE model generated

24. Metal width from VCR
With the procedure described before the width of the metal line is difficult to obtain if the length is not known
Virtuoso Custom Router (VCR) from Cadence
VCR allows automatic and manual routing between the devices on a circuit
Routing done after the devices are placed using a placement tool

25. Metal width from VCR
Placement tool works to place the devices in the circuit at the optimum places from schematic
Routing tool then draws metal and poly lines between them
The lines are drawn depending on the dimension requirements from the user, and these values are documented in the device rules file in VCR

26. Layout as created by VCR
Layout as created by Virtuoso Custom Router

27. devicelib.rules file from Virtuoso Custom Router
Rules file from VCR
devicelib.rules file from Virtuoso Custom Router

28. Calculated Current density values
Parameter
Value
Units
wdith, W
3 E -6 .m
J EM(T m)
E 8
A .m-2
Jrms (T m)2
E 21
Jrms
4.712 E 10 r
1.23 E -3
Jpeak
134.3 E 10
Jcalc
96.87 E 10
Current density values calculated

29. Verification of Current Densities
Account for temperature, characteristics of the process, and materials parameters and relate it with the current density that has been measured
Relation between an acceptable current density Jcir(T) at an actual tempereature T and a material-dependent maximum current density Jpeak (Tref) at a given reference temperature Tref,
with Q denoting experimentally determined activation energy, k denoting the Boltzmann’s constant, Tref usually 100 C for silicon, and
T the working temperature
| Jcir(T)| ≤ | Jpeak (Tref)|.exp ( - (Q/nk Tref)(1-( Tref /T)))

30. MTTF Calculations
Mean Time To Failure, MTTF, of a system is the expected time a system will operate before the first failure occurs
The MTTF of a conductor under a constant current stress is expressed by
MTTF = AJ-n exp {Ea/ kT}
Where
Ea - Activation Energy,
J - Current density,
T - Temperature in degrees Kelvin
A - constant depending on geometry and material parameters – scaling factor
K - Boltzmann constant,
n - constant ranging from 1 to 7

31. MTTF Calculations Three associated problems in electromigration
- Joule Heating (JH)
- Current crowding
- Material reactions
If the reliability of a system can be expressed in terms of a failure parameter, then it should be possible to express it as a numerical index which could be seen as a fitness of the design created

32. Conclusion and future works
A simple method for electomigration analysis was devised and the current density violations were checked for MTTF calculations
Once these analysis confirms that current densities do not exceed the limits, the mean time to failure (MTTF) calculations are done for the interconnects
The future works for this project include,
- Design and simulation of some basic test circuits for the electomigration analysis and MTTF calculations.
- Extraction of interconnect width at the layout level for variable width interconnect circuits, using metal line parasitic either from Cadence tools.

33. Conclusion and future works
- Formulating a capacitance extraction technique for VLSI circuits which have the overlap, fringing and other intrinsic capacitance values, which might be used for the interconnect width estimations
- Developing a PERL script for incorporating the electromigration analysis – current density and temperature violation checks, and the MTTF calculations.
- Determination of current crowding and hot spots at different places in a circuit for estimating the failure time. By this way the MTTF estimations can be done for a specific number of metal lines surrounding the hot spots.
- Extending this work for circuits from industry and performing analysis and calculations for specified interconnects alone for processing time optimization.