1. CSIT 301 (Blum)1 Processor Specs

2. CSIT 301 (Blum)2 Micro-architecture A processor’s architecture refers to its instruction set, the number and type of registers, and memory- resident data structures (e.g. stacks) that are available to a programmer (at least at the assembly level). A processor’s micro-architecture refers to the hardware implementation of the architecture (the transistors). Backward compatibility is within the architecture (which is more of a logical level). The micro- architecture (implementation) may change dramatically and is not necessarily compatible with previous versions.

3. CSIT 301 (Blum)3 Package Type (Pentium 4)

4. CSIT 301 (Blum)4 Package Type (Core2)

5. Package Type (i7) CSIT 301 (Blum)5

6. http://ark.intel.com/products/63696/Intel-Core-i7-3960X-Processor- Extreme-Edition-%2815M-Cache-3_30-GHz%29 CSIT 301 (Blum)6

7. 7 Form Factor and Package The term form factor applies to many devices including processors. It refers to their size and shape. And in the case of processors it also includes how they connect to the motherboard. –The motherboard has a slot or socket. A related term is the “package” — an enclosure for a chip (integrated circuit).

8. CSIT 301 (Blum)8 Pinning The pins or leads are how a chip interfaces with the outside world. There are various ways to arrange the pins on a chip. Furthermore, several chips can be brought together into unit called a module (common in memory).

9. CSIT 301 (Blum)9 PGA/DIP/SIP PGA: pin grid array, chip in which the pins are located on the bottom in concentric squares. –Used in some microprocessors. DIP: dual in-line package, rectangular chip with two rows of pins, one on each side. SIP: single in-line package, chip with pins protruding from one side

10. Two basic issues “Pins”: How does the processor connect? How many “pins” are there? How big are they? How are they arranged? How can we keep them from bending, etc.? Heat: How do we let the processor dissipate heat? CSIT 301 (Blum)10

11. CSIT 301 (Blum)11 SEPP (OLD!) Single-Edge Processor Package With the S.E.P.P. form factor, the processor is not completely covered by the black plastic (as in S.E.C.C.and S.E.C.C.2). The circuit board (substrate) can be seen from the bottom side. An out-dated processor packaging scheme.

12. CSIT 301 (Blum)12 SECC (OLD!) Single Edge Contact Connector With the S.E.C.C. form factor, processors have a plastic shroud covering with an active heatsink and fan. Identifiable by the goldfinger contacts which in this case are inside of the plastic housing. Another out-dated processor packaging scheme.

13. CSIT 301 (Blum)13 SECC2 (OLD!) As with SECC, with SECC2 the processors have a plastic housing with an active heatsink (means it has a fan). It is distinct from SECC in that the goldfinger contacts are exposed.

14. CSIT 301 (Blum)14 Heat Recall that in the history of processors the number of transistors continues to grow (Moore’s Law) while the relative size of the chip stays fixed. With more transistors carrying current, more heat is produced (within the same area). Various developments have occurred to deal with the issue of heat. –Reduction in the working voltage (5V  3.3V  2V). –Introduction of the heatsink and fan.

15. CSIT 301 (Blum)15 Heat Sink The computer has had a fan for some time to deal with heat. But starting with the 486, the processor needed special consideration. A heat sink is an element designed to take heat away from the processor. In this case, heat is dissipated mainly via convection, the heat is transferred to the nearby air and is carried away with the air as it moves. –Convection is why a breeze feels nice on a hot summer day.

16. CSIT 301 (Blum)16 Desired Effects A heat sink should have a large surface area since this is where the heat is transferred to the air. But the heat sink should not block the air flow since this is how the heat is carried away. Heat sinks often have very strange shapes to try to maximize these two competing effects. –Typically made of Aluminum –May have “fins”

17. CSIT 301 (Blum)17 Heat Sinks

18. CSIT 301 (Blum)18 Passive and Active All modern processors have a heat sink. Some also require a fan. –Without a fan: passive heat sink –With a fan: active heat sink Because the heat sink’s purpose is to dissipate heat, it is important that the heat can get from the processor to the heat sink. The material “gluing” the heat sink to the processor must conduct heat well. A heat slug is a piece of metal that connects the processor core to the processor package and/or heatsink.

19. Thermal paste CSIT 301 (Blum)19

20. Liquid Cooling CSIT 301 (Blum)20

21. Advances in fans? Today the fans have multiple speeds and the processor monitors its own temperature and adjusts the fan speed accordingly. Customers complain about the noise of the fan. CSIT 301 (Blum)21

22. Varying Speed I: Turbo Boost CSIT 301 (Blum)22 Recall that there is a connection between speed and power. Speed is measured in Hertz (cycles per second) and power is measured in Watts (Joules per second). Furthermore, power (once used) becomes the rate at which heat is generated.

23. Varying speed II: Intel SpeedStep CSIT 301 (Blum)23 Especially with the growing emphasis on mobile computing, power consumption has become an important factor.

24. CSIT 301 (Blum)24 PPGA Plastic Pin Grid Array With PPGA the processors have pins arranged in a square pattern. They fit into Socket 370 motherboards. Look for the square pattern (Pin Grid Array) on the bottom. Slot connectors do not have pins.

25. CSIT 301 (Blum)25 FC-PGA Flipped-Chip Pin Grid Arrays The chip is designed so that the “core” processor, which is the part that gets the hottest, is on top (closer to the heat sink). Also fits into a socket 370 motherboard. But it must be a FCPGA compliant motherboard for FCPGA processor to work.

26. CSIT 301 (Blum)26 Pentium 4 Form Factors Pentium 4’s also come in a FCPGA form factor. –The package uses 478 pins, which are 2.03 mm long and.32 mm in diameter. FCBGA (Flip Chip Ball Grid Array) –Instead of pins, FCBGA uses small balls, which acts as contacts for the processor. Pins bend, ball don’t. –The package uses 479 balls, which are.78 mm in diameter.

27. CSIT 301 (Blum)27 The LGA "Intel’s new LGA, or Land Grid Array, 775 processor socket takes a step away from traditional implementations in that the package no longer features pins, rather the bottom of the LGA 775 processors only have small gold contacts. With the LGA package, Intel has moved the pins into the bottom portion of the processor socket, something that will make installation of the processor easier in that there is no need to watch for bent pins on the package...although it will make it more difficult as well. You no longer need to worry about bent or damaged pins on the processor, rather now you have to worry twice as much about bent pins within the processor socket itself." http://rootprompt.org/article.php3?article=7115

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29. FC-LGA-2011 – 2011 is the number of connections not a year CSIT 301 (Blum)29

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31. TDP: Thermal Design Power CSIT 301 (Blum)31

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33. T CASE CSIT 301 (Blum)33

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35. VID CSIT 301 (Blum)35

36. Socket R uses QPI to connect the CPU to additional CPUs. QPI: QuickPath Interconnect – replacement for FSB (FrontSide Bus) CSIT 301 (Blum)36

37. DMI 2.0 is used to connect the processor to the PCH. DMI: Direct Media Interface Northbridge to Southbridge link CSIT 301 (Blum)37 Note some Northbridge functions have moved onto the processor.

38. DMI 2.0 is used to connect the processor to the PCH. PCH is Platform Controller Hub – reassigned Northbridge- Southbridge functionality. CSIT 301 (Blum)38

39. FDI CSIT 301 (Blum)39

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42. Bus/Core Multiplier aka CPU Multiplier CSIT 301 (Blum)42

43. PCI Express (PCIe) CSIT 301 (Blum)43

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45. PCIe (cont.) CSIT 301 (Blum)45

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47. CSIT 301 (Blum)47 Internet Streaming SIMD Extensions SSE is an acronym within an acronym: It stands for Streaming SIMD Extensions, where SIMD is Single Instruction Multiple Data SSE consists of 70 SIMD instructions for integer and floating-point operations. It helps with high resolution images, audio and video viewing, speech recognition etc. The Pentium 4 actually used SSE2. SSE2 adds 144 new instructions.

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50. SSE4 (Cont.) CSIT 301 (Blum)50

51. AVX: Advanced Vector eXtensions CSIT 301 (Blum)51

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53. Hyper-Threading CSIT 301 (Blum)53

54. Hyper-Threading Technology CSIT 301 (Blum)54

55. CSIT 301 (Blum)55 Intel® Wide Dynamic Execution A combination of techniques (data flow analysis, speculative execution, out of order execution, and super scalar) that enables the processor to execute more instructions in parallel. –Pipelining ideas Delivers more instructions per clock cycle to improve execution time and energy efficiency.

56. Same for Nehalem The Nehalem architecture (45-nm) allowed up to four instructions per clock cycle Has improved “out of order” instruction handling –They have made the window/buffer of instructions to be examined for possible pipelining or parallelizing CSIT 301 (Blum)56

57. CSIT 301 (Blum)57 Pipelining Recall that to execute an instruction, one must fetch it, decode it, fetch any data required, execute the instruction, write the answer to the appropriate place and possibly look for an interrupt requests that might have occurred during the previous. In pipelining a processor can begin executing a second instruction before the first has been completed. Thus, many instructions are in the pipeline at the same, though at various processing stages.

58. CSIT 301 (Blum)58 Pipelining The pipeline is divided into segments. Each segment can perform its duty at the same time as the other segments. When a segment completes its task, it passes the result to the next segment and fetches the next operation from the preceding segment. Once a feature of only high-end processors, now pipelining is standard. –A Pentium had up to six instruction in the pipeline.

59. CSIT 301 (Blum)59 Hyper-Pipelined Technology Pentium 4’s Hyper-pipelined technology uses a 20-stage pipeline. Having so many instructions in the works can be a problem if the program branches and one has the wrong instructions in the pipeline. For long pipelines to be effective there must be good “branch prediction.” BPU – Branch Prediction Unit

60. CSIT 301 (Blum)60 Intel® Wide Dynamic Execution (Cont.) Wider execution core allow each core to fetch, dispatch, execute and retire up to four full instructions simultaneously. More accurate branch prediction Deeper instruction buffers for greater execution flexibility

61. Nehalem The Nehalem micro-architecture (45-nm) added a “Second-Level Branch Prediction Target Buffer” improves prediction and makes the situation better when the prediction is incorrect. CSIT 301 (Blum)61

62. CSIT 301 (Blum)62 Intel® Advanced Smart Cache The Intel Advanced Smart Cache is a multi- core optimized cache. Reduces latency to frequently used data –Improves performance and efficiency by increasing the probability that each execution core can quickly access data.

63. CSIT 301 (Blum)63 Intel® Smart Memory Access Intel Smart Memory Access optimizes the use of the available data bandwidth from the memory subsystem. Includes an important new capability called "memory disambiguation," –which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed. –(I.e. get what you need when you need it)

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65. CSIT 301 (Blum)65 Intel® Virtualization Technology Intel® Virtualization Technology (Intel® VT)¹ improves traditional software-based virtualization solutions. –“These integrated features give virtualization software the ability to take advantage of offloading workload to the system hardware, enabling more streamlined virtualization software stacks and ‘near native’ performance characteristics.”

66. CSIT 301 (Blum)66 Virtualization Using virtualization, one computer system can function as multiple "virtual" systems. –Can run multiple operating systems (simultaneously) –One machine being used as a number of independent virtual machines. –Allows consolidating and balancing of multiple workloads on one physical server system. –Lowers hardware acquisition costs –Improves data center performance efficiency.

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68. CSIT 301 (Blum)68 Execute Disable Bit Intel's Execute Disable Bit allows the processor to distinguish between areas in memory where an application can execute and where it cannot. Can be used to disable certain worm attacks.

69. Intel TXT (Trusted eXecution Technology) CSIT 301 (Blum)69

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72. New AES (Advanced Encryption Standard) Instructions CSIT 301 (Blum)72

73. CSIT 301 (Blum)73 New AES (Advanced Encryption Standard) Instructions

74. CSIT 301 (Blum)74 Intel® Advanced Digital Media Boost Intel® Advanced Digital Media Boost is a feature that significantly improves performance when executing Intel® Streaming SIMD Extension (SSE/SSE2/SSE3/) instructions. And now SSE4. Accelerate video, speech and image, photo processing, encryption, financial, engineering and scientific applications. Enables 128-bit instructions to be executed at a throughput rate of one per clock cycle, doubling the speed of previous generations.

75. Quick Sync Video CSIT 301 (Blum)75

76. Intel Clear Video CSIT 301 (Blum)76

77. InTRU CSIT 301 (Blum)77

78. CSIT 301 (Blum)78 References PC Hardware in a Nutshell, Thompson and Thompson http://www.webopedia.com http://www.intel.com http://www.anandtech.com http://www.mbreview.com/lga775.php

79. References (Cont.) http://www.intel.com/technology/architectu re-silicon/next-gen/whitepaper.pdf http://en.wikipedia.org/wiki/SSE4 CSIT 301 (Blum)79