1. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 1 GLAST Large Area Telescope: B. Estey, G. Haller SLAC xxxx LAT Quality Engineer haller@slac.stanford.edu (650) 926-4257 esteyb@slac.stanford.edu (650) 926-8531 Gamma-ray Large Area Space Telescope PDU & GASU Manufacturing Readiness Review (MRR)

2. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 2 Contents Presentation I (G. Haller) –DPU & GASU Module Description –Changes since CDR –Design and Test Documentation –Engineering Module Validation Presentation II (B. Estey) –Parts, Materials & Processes –Procurement Status –Manufacturing Facilities –Manufacturing Flow Plan –Quality Assurance Plan –Configuration Management –Manufacturing Issues/Concerns Presentation III (xxxxx) –Quality Assurance Plan

3. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 3 GLAST Large Area Telescope: G. Haller SLAC haller@slac.stanford.edu (650) 926-4257 Gamma-ray Large Area Space Telescope PDU & GASU MRR Part I

4. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 4 LAT Electronics 3 Event-Processor Units (EPU) (2 + 1 spare) –Event processing CPU –LAT Communication Board –SIB Spacecraft Interface Units (SIU)* –Storage Interface Board (SIB): Spacecraft interface, control & telemetry –LAT control CPU –LAT Communication Board (LCB): LAT command and data interface 16 Tower Electronics Modules & Tower Power Supplies * Primary & Secondary Units shown in one chassis Power-Distribution Unit (PDU)* –Spacecraft interface, power –LAT power distribution –LAT health monitoring Global-Trigger/ACD-EM/Signal-Distribution Unit* TKR CAL TKR Front-End Electronics (MCM) ACD Front-End Electronics (FREE) CAL Front-End Electronics (AFEE)

5. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 5 PDU & GASU Mounted on LAT Show picture of PDU and GASU on test-bed TEM TPS CAL

6. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 6 EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking Primary and Redundant Circuits in one Enclosure –Receives Primary and Redundant 28-V from spacecraft –Each, primary and redundant DPU can select between primary and redundant spacecraft power –Filters 28V –Turns on/off 28V to 16 towers and 3 EPU’s under program control –Protects PDU and down-stream circuits from over- current and under-voltage situatations Over-current via poly-switches Under-voltage via custom circuit in each power- on branch –Receives command/clock from GASU –Digitizes voltaes/temperatures from > 150 sources Includes temperatures from radiators, GRID used for thermal control –Reads back data to SIU via GASU –Provides PDU DAQ voltage and temperature analog data to spacecraft for monitoring Power Distribution Module (PDU)

7. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 7 EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking Primary and Redundant Circuits in one Enclosure –Contains two types of circuit card assemblies GASU Power Supply CCA GASU DAQ Board CCA –GASU Power Supply Receives 28-V supply voltages for –Primary and redundant DAQ board, generates 3.3V and 2.5v ACD power-switch circuit for ACD FREE cards –Filtering –GASU DAQ Board Contains 9 FPGA’s Includes Command Response Unit, Fan-out and fan-in of commanding to 16 TEMs, PDU, EPU’s, ACD Includes Global Trigger Logic Includes LAT Event-Builder Logic Includes command/control/read-back for ACD sub-system Includes power-control for ACD FREE Boards GASU

8. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 8 Changes since CDR PDU –Creation/Modification of PDU FPGA code –Power-on circuit was modified to include under-voltage shut-off to protect MOS power-on switches –In-rush current limits modified to loads GASU –Code in 9 FPGA’s were modifed/finalized and bugs fixed –ACD power-on low-frequency system clock selection added –ACD power circuits replaced with circuit to protect for over- current and updated ICD interface voltage/current requirements

9. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 9 Peer Review RFA Status Are there any?

10. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 10 PDU (replace spread-sheet below)

11. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 11 GASU

12. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 12 ASICs GLTC radiation and qualification –SEL and SEU ok –TID is scheduled for next week in Italy –Qualification at GSFC will start after the radiated ASICs are tested on the test-setup, so it can be shipped to GSFC. –ASICs for flight boards are being burned in and tested, full quantity required ready within one week.

13. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 13 Engineering Model Design Validation PDU & GASU –Tested on bench and on test-bed Functionality and performance validated on test-bed 16 TEM/TPS connected to EM PDU and GASU and to SIU, EPU’s and ACD FREE’s –Validated over frequency and voltage margins –GASU used in ACD G3 test-stands at GSFC –Limitations No temperature tests performed on PDU or GASU Flight boards checked for flight component foot-prints PDU: flight board loaded with some flight components and tested GASU: no flight board tested yet

14. GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 14 Issue GLTC ASIC (GASU) –ESD sensitivity about 200V Assembly controls to < 50V Trigger FPGA code (GASU) –Only recently finalized and tested on test-bed Flight FPGA’s slower –Could not burn 9 flight FPGA’s for use on non-flight board –Finite risk Omnirel fixed-voltage regulator (PDU) –Was recalled and we are waiting for replacements, promised end of February Transient Suppressor diode did not pass DPA (PDU) –Ordered S-class replacements which were in stock PCB’s did not pass coupon testing (PDU) –Fabricated new batch, is at GSFC for coupon testing