1. Unit 12 Registers and Counters Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. 22004/05/17Registers and Counters Outline 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip-Flops Flip-Flops 12.6Derivation of Flip-Flop Input Equations -- Summary -- Summary

3. 32004/05/17Registers and Counters Counters for Other Sequences The sequence of states of a counter is not in straight binary order. State graph

4. 42004/05/17Registers and Counters State Table

5. 52004/05/17Registers and Counters Input for T Flip-Flop

6. 62004/05/17Registers and Counters Derivation of T Inputs

7. 72004/05/17Registers and Counters Counter Using T Flip-Flops

8. 82004/05/17Registers and Counters Timing Diagram

9. 92004/05/17Registers and Counters State Graph for Counter

10. 102004/05/17Registers and Counters Summarized Procedure 1.Form a state table which gives the flip- flop states for each combination of present flip-flop states. 2.Plot the next-state maps from the table. 3.Plot a T input map for each flip-flop. 4.Find the T input equations from the maps and realize the circuit.

11. 112004/05/17Registers and Counters Counter Design Using D Flip-Flops For a D flip-flop, Q + = D The D input map is identical with the next-step map. The D input map is identical with the next-step map.

12. 122004/05/17Registers and Counters Counter Design Using D Flip-Flops