1. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida1 Muon Track-Finder Trigger Darin Acosta University of Florida June, 2002

2. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida2 Muon Track-Finding   Link trigger primitives into 3D tracks Measure p T, , and  in non-uniform fringe field Send highest quality candidates to Global L1 Partitioned into 60° sectors that align with DT chambers

3. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida3 Strip FE cards Wire FE cards Muon Port Card (Rice) MPC Sector Receiver/ Processor (U. Florida) OPTICAL SR/SP SP CSC Muon Sorter (Rice) Global  Trigger DTRPC FE Global L1 2  / chamber 3  / port card 3  / sector 44 44 44 44 LCT Trigger Motherboard (UCLA) Wire LCT card In counting house TMB LCT RPC Interface Module RIM On-Chamber Trigger Primitives 3-D Track-Finding and Measurement Combination of all 3 Muon Systems CSC Muon Trigger Scheme EMUTrigger

4. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida4 Scope of CSC Track-Finder Prototype version tested Fall 2000: New version (SR/SP combined) Board# unitsResponsibility MPC48Rice Sector Receiver 24UCLA Sector Processor 12Florida Clock and Control Board 6Rice CSC Muon Sorter 1Rice Crates, Backplanes 6Florida DDU readout 1Florida/Ohio State Board# unitsResponsibility MPC48Rice SR/SP12Florida Clock and Control Board 1Rice CSC Muon Sorter 1Rice Crates, Backplanes 1Florida DDU readout 1Florida/Ohio State Baselined with 24 crates, reduced to 6 in 1998, now 1:

5. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida5 Prototype Track Finder Tests Focus during FY 2000 was on producing and testing prototypes of all Track-Finder components (except the CSC Muon Sorter) Sector Processor: UFlorida Sector Receiver: UCLA Muon Port Card: Rice Clock and Control Board: Rice Channel-Link backplane: UFlorida Integration tests of the complete system yielded 100% agreement between hardware and software for random and simulated physics events Port Card FIFO Sector Receiver FIFO Sector Processor FIFO DAQ System (VME, Bit3 Controller, PC running Windows NT) 100m Optical Links Custom Back plane FIFO Results included in Trigger TDR

6. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida6 Sector Receiver Prototype Optical Receivers and HP Glinks SRAM LUTs Front FPGAsBack FPGAs UCLA Receives and formats track segment data

7. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida7 Extrapolation Units XCV400BG560 Final Selection Unit XCV150BG352 Bunch Crossing Analyzer XCV50BG256 Track Assemblers 256k x 16 SRAM Assignment Units XCV50BG256 & 2M x 8 SRAM Sector Processor Prototype 12 layers 10K vias 17 FPGAs 12 SRAMs 25 buffers Florida Links track segments into 3D tracks, selects best three tracks, measures momentum

8. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida8 1 st Track-Finder Crate Tests Sector Processor (Florida) Sector Receiver (UCLA) Clock Control Board (Rice) Bit3 VME Interface CustomChannelLinkBackplane(Florida) Muon Port Card (Rice) 100m optical fibers Very successful, but overall CSC latency was too high -- New design in 2001 improves latency Prototype crate for original six crate design

9. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida9 Single Track-Finder Crate Design with 1.6 Gbit/s optical links Reduces processing time from 525 ns (old design) to 175 ns Total Latency ~ 15 Bx (from input of SR/SP card to output of MS card) Crate Power Consumption ~ 1000 W 16 Optical connections per SR/SP card Custom Backplane for SR/SP  CCB and MS connection New Track-Finder Crate Design SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP CCB BIT3 Controller SR/SP Card (3 Sector Receivers + Sector Processor) (60  sector) Clock and Control Board Muon Sorter To Global Trigger From Trigger Timing & Control From MPC (chamber 4) From MPC (chamber 3) From MPC (chamber 2) From MPC (chamber 1B) From MPC (chamber 1A) To DAQ MS

10. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida10 CSC Track Finder Backplane Design Approved – Technology same as EMU peripheral crates Standard VME 64x J1/P1 backplane Standard VME J2/P2 backplane Muon sorter Clock and control SRSP 6SRSP 5SRSP 4SRSP 3SRSP 2SRSP 1 SRSP 12 SRSP 11 SRSP 10 SRSP 9SRSP 8SRSP 7 Custom GTLP 6U backplane Rice Florida These SRSP feedthru connectors are for DT information exchange via transition board GTLP backplane avoids latency penalty of previous Channel-Link backplane (~3BX)

11. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida11 SR/SP 2002 Board Layout

12. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida12 SR/SP 2002 Design Status Schematics nearly complete: Sector Receiver Front FPGAs (5 total) Choice: XC2V1000-FF896C with 432 user I/Os Sector Processor Main FPGA Choice: XC2V4000-FF1152C with 824 user I/Os Placed on mezzanine card (design started) Firmware written in “Verilog++”, validated by simulation VME & control interface FPGA Choice: XC2V250-FG456C with 200 user I/Os DAQ Interface FPGA Choice: XC2V250-FG256C with 172 user I/Os SRAM: 51 SRAM chips (>64MB) for Look-up functionality Layout to commence soon Board will be dense! (Merger of 4 boards, but I/O ~same)

13. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida13 New Design Reduces Latency Optical receivers Front FPGAs Lookup tables Channel link transmitters Channel link receivers Bunch crossing analyzer (not implemented) Extrapolation units 9 Track Assembler units (memory) Final selection unit 3 best out of 9 Pt precalculation for best 3 muons Pt assignment (memory) Sector Receiver st.1 Sector Receiver st.2,3 Sector Receiver st.4 1 4 1 2 3 2 3 3 2 Optical receivers Front FPGAs Lookup tables Bunch crossing analyzer (not implemented) Extrapolation units 9 Track Assembler units Final selection unit 3 best out of 9 Pt precalculation for 9 muons Pt assignment (memory) 1 0 1 1 1 1 1 1 Output multiplexor Sector Processor SR/SP board Sector Processor FPGA First prototype dataflowPre-production prototype data flow Latency Total: 21 BX Total: 7 BX To Muon Sorter From Muon Port Cards To DT

14. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida14 VME J1 CONNECTOR CUSTOM BACKPLANE 9U * 400 MM BOARD CONNECTORS TO GMT LVDS DRIVERS CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO VME INTERFACE SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 CABLES TO GLOBAL MUON TRIGGER CRATE GTLP TRANSCEIVERS New Muon Sorter Design (Rice) Reduced to single board -- reduces latency, cost New: Will use common Xilinx mezzanine card with Sector Processor

15. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida15 PIPELINE MUON 1 LUTs PIPELINE MUON 2 DFF SORTER “4 OUT OF 36” MUON 1 CCB SP 1 SP 2 DFF FIFO FIFO VME MUX VME SP 12 VME MUON 2 VME FIFO... DFF FIFO VME MUX PIPELINE MUON 3... VME DFF FIFO DFF VME FIFO VME DFF FIFO MUON 3 MUON 4 LUTs VME LUTs VME 144 CCB INTERFACE Sorter FPGA

16. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida16 CCB for Track Finder Crate Same CCB for peripheral (EMU) and Track Finder crates 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far 15 boards are assembled and tested 2 boards will be used for Track Finder tests (UF&Rice) TTCrx mezzanine board

17. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida17 PersonnelPersonnel Professors Darin Acosta (Florida), Robert Cousins (UCLA), Paul Padley (Rice) Postdocs Song Ming Wang (Florida), Slava Valouev (UCLA) Students Bobby Scurlock (Florida), Jason Mumford (UCLA) Engineers Alex Madorsky (Florida), Mike Matveev (Rice), Ted Nussbaum (Rice) Collaborating engineers (all PNPI) Victor Golovtsov, Lev Uvarov

18. US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida18 ConclusionsConclusions First Track Finder system prototyped successfully in Fall 2000 Exact match to CMS OO simulation package Second generation pre-production prototype is well underway with significant improvements Present and future activities 2001: R&D on optical links, FPGA logic, memory look-ups, backplane technology, and DAQ readout 2002: build the 2 nd generation prototype 2003: test with multiple CSC chambers, cosmic rays and/or structured beam, tweaks for final design (if necessary) 2004: full production 2005: installation No trouble expected: all-digital system with off-the-shelf components, well-defined internal and external interfaces, and a stable and capable engineering team