1. Linac Marx Modulator Update Trevor Butler & Howie Pfeffer 2/25/2015

2. Overall Status Update Finished up Marx 9 Cell Design Started to build 25 cell Marx – Determined to build 28 cell Marx instead – Determined many components will need to be redesigned for many reasons Air Flow concerns Corona concerns Voltage Standoff concerns Personal Safety (floating metal in design) Changed design to 28 cell version for initial testing, then followed by 54 cell version – Determined that control system original intended for both the original 25 and 54 cell designs would not be feasible in the short term. – Decided to build a larger version of the control system original designed for the 9 cell Marx test for both 28 and 54 cell design

3. 9 Cell Marx Final Design Finalized design of 9 cell Marx modulator Upgraded the following components from the original 9 cell prototype – Replaced one snubber capacitor with two – Built gate clamp circuit – Finalized b-dot coil design – New low inductance stripline Ran all 9 cells in both with and without PWM – Achieved much greater than 20kV/us slew rate with all nine cells fired simultaneously (15 kV/us spec) – Achieved the +/- 25 ripple specification. Have since determined the ripple specification should have been listed as a voltage over frequency since the frequency response of the tube / accelerating cavity will filter this response ripple at higher frequencies. Results – Determined importance of cell timing accuracy to enable low ripple operation. This will require accurately measuring each cell delay time (at full load current) to compensate. – Was able to reduced short circuit current to 1700 Amps for the 9 cells using the gate clamping circuit

4. 600V CPS, 2.5V ref Ch.1 Stripline output voltage Ch.2 Filter output voltage Ch.3 Stripline output current (100A/V) (includes filter current) 900V CPS, 2.5V peak ref. Ch.1 Stripline output voltage Ch.2 Load Current (100A/V) Ch.3 Cell 1 gate clamp circuit active 900V CPS, 2.5V peak ref. Ch.1 Stripline output voltage Ch.2 Load Current (100A/V) Ch.3 Cell 1 gate clamp circuit active 900V CPS, 2.5V peak ref. Ch.1 Stripline output voltage Ch.2 Load Current (100A/V) Ch.3 Cell 1 gate clamp circuit active 550V CPS, 2.5V ref. Spark gap triggered Ch.1 Stripline output voltage Ch.2 Common voltage Ch.3 Stripline output current (100A/V) Ch.4 Cell 1 Gate clamp active 600V CPS, 2.5V ref Ch.1 Stripline output voltage Ch.2 Filter output voltage Ch.3 Stripline output current (100A/V) (includes filter current) Filtered Voltage Stripline Voltage Stripline Current Filtered Voltage Stripline Voltage Stripline Current Common Voltage Cell 1 Gate Clamp Stripline Current Load Current Stripline Voltage Load Current Stripline Voltage Load Current Stripline Voltage

5. 25/54 Cell Original Design Originally planned on developing control system for the 25/54 using and FPGA controlling the CPLD’s, which in turn, fire and charge the IGBT’s After investigating the technical requirements, decided that a SoC (system on a chip) using the Altera Cyclone V chip would be the only option – This option would require a long time (> 1 year) to design, program, test, and debug. – It was desired to be able to do high voltage testing on both the 25 and 54 cell versions, which can’t wait for this development time – Using a modified version of the original 9 cell control system would work for larger versions Would not have the timing accuracy of the SoC FPGA design Would require signals to be converted from A/D and back using D/A converters to do the controlling Would not be able to real-time feedback, but may be able to do some analog feedback Decided to switch over to a 28/54 cell design

6. 28/54 Cell Modified Design Determined that building the 54 cell version on top of the 25 cell version would not be feasible – Air Flow concerns focus each cell air through cooling fins and not around – Corona concerns Round all corners of existing heat sinks to prevent corona – Voltage Standoff concerns Modify cabinet to have greater than 6” between both walls and any Marx cells at high voltage Will be able to reuse the existing enclosure for the lower voltage version – Personal Safety (floating metal in design Will replace all metal shelving pieces, screws, and support structure with plastics to reduce corona and prevent ungrounded metal from floating up to high voltage and creating a potential shock hazard Decided to use the existing cabinet and build a 28 cell version (4 rows with 7 cells per row) – Will test with both PWM and non-PWM cell simultaneously, similar to the final design – Will reuse the existing control cards that have been developed – Will require new CPLD to be installed to handle more logic elements than the present 1500 limitation – Will require backplane to be designed for both 28 and 54 cell versions – Will require building new main control card to interface between all cell and future FPGA This 28 cell version may be able to operate on LRF1 – Depends on success of design to hold off voltage, prevent corona, and cool efficiently – Depends on gain of tube in LRF1

7. 28 Cell Version Changes from Existing Design 7 cells wide instead of 9 Only 4 rows tall instead of 6 More space on front of cells Lexan on backplane for isolation Self supported structure (Does not relay on screws for strength) Two fans for better cooling

8. Dual Development of 28 / 54 Cell Design Testing the Marx topology at a lower voltage (28 cells * 900 Volts ~ 25 kV), a the lessons learned could would be applied to the 54 cell version The 54 cell version will be built into a newly designed cabinet – Larger Voltage Standoff between walls and cell – New Lexan based shelves – Mounting brackets with no metal screws – Increased airflow to each cell This cabinet will be designed after corona testing of the cells in 28 cell version By building both the 28 cell and 54 cell simultaneously, then as the 28 cell is being tested, the 54 cell construction can start. The control cards developed for the original 54 cell version will still work with the modified 28 and new 54 cell modulators. – Many of the control cards are complete – A new Preliminary FPGA Control Interface Card will be built to interface with both the 28 and 54 cell designs, and be upgradable (by adding a additional FPGA card) to the final control system – This design will allow for the cards developed to be used in final system without any additional circuit board design

9. Control Card Status Task Name Drawing NumberSchematicLayoutPartsAssembled SchematicLayout28/54 28542854 IGBT Gate Driver0231-EC-2819300231-BD-281931100% 50%0% 18 Cell Driver0231-EC-2819940231-BD-281995100% 0% Status Input0231-EC-2819960231-BD-281997100% 50% Status Sum0231-ED-2819980231-BD-281999100% 50%10% Charge control0231-EE-4980000231-BD-498001100% 50% Control Backplane0231-EE-4980040231-BD-49800575%0% Preliminary FPGA Control Interface0231-EE-4980060231-BD-49800775%0% Analog Compartor Interlock0231-ED-4980200231-BD-498021100%80%0% Charge Diode and Gate Clamp Circuit0231-EB-4980300231-BD-498031100% 0% PLC Level InterfaceTBD 0% Inerface to Analog CompartorTBD 0% Interface with FPGATBD 0% Many Cards have been designed, layout created, parts order, and built Presently Finishing up the drawings for the two most complex cards, the FPGA Control Interface Card (with CPLD) and the Backplane Plan to have the drawings into EE Support drafting within two weeks to start layout of boards (labor is promised) 3 interface cards (only a few components per card) need to be designed and layout create, but since they are simple, they should only take an addition 2-3 weeks to design, layout, and order parts

10. Corona Testing Tested Heatsink without any polishing or rounding of corners and it failed the test Tested Heatsink with rounded edges and passed test Using multiple jumpers, create 3 complete cell version to test at high voltage. – Passed at 36 kVrms (50 kVpeak)

11. Future work Test the cells at full loading conditions – 350 amps, at 15 Hz, with full PWM switching Test the Capacitor Charging Supply from Lumina power to determine if it will work for these design – Could be used for either the 9 cell or 28 cell versions – More would need to be purchased for 54 cell design Design Charging Supply Controller Interface Chassis Design PLC and touch panel interface for operation into existing RF systems Build charging supply control interface for testing into development area and in operational stations Order and build additional 35 cells to complete 54 cell design in parallel with 28 cell design Finish Control Card Design and Layout Build remaining cells and control cards (one item, but a lot of work involved in this line) Corona testing of the 28 cell version Successfully regulate cavity gradient on operating station – Will likely require many rounds of studies to check versus ideas – It may require more than feed-forward and learning to operate

12. One option for testing Marx Considered Many Options for testing Likely will place in the hallway Minimizes cabling length Only 66” hallway clearance (need 64”) Fire Safety approved this location Will be difficult to access when blocking main door May need to consider converting strip line output to coaxial output

13. Different cavity gradient regulation schemes Direct Gradient Analog Feedback Presently used to regulate our vacuum tube modulators Op-Amp feedback loop with adjustable proportional gain Advantages – Simple in design, and robust in operation – Direct feedback cancels out any pulse to pulse variations as it noticed significantly on LRF1 Disadvantages – Lack of real time tuning and optimization via ACNET. – Interfacing with existing LLRF Learning Algorithm can be problematic and require frequency tuning Feed-Forward Operation (often confused with Learning) Uses a system model of the load (the 7835 triode, accelerating cavity, and beam intensity) to predict the required amount of voltage to get the desired gradient level Advantages – Can act as a first guess before implement any learning or feedback Disadvantages – Almost impossible to get perfect model. – Even if you could, it could drift over time, requiring constant tuning to stabilize gradients

14. Different cavity gradient regulation schemes Learning Operation Learns the waveform error from pulse to pulse, placing correction on next pulse If the Learning Operation is used on top of the Feed-Forward loop, then the system would have less error to correct Advantages – Able to learn out slow process (Aging of tube, drifting of cavity frequency, Disadvantages – Unable to regulate voltage within the pulse. Real-Time Feedback Realtime operating system, like the SoC FGPA topology Error between the cavity fields is calculated in realtime and the error is sent to the PWM for correction within the pulse Advantages – Able to Control cavity fields within the pulse, accounting for pulse to pulse variations Disadvantages – Complex to design – Long development time

15. Testing on LRF2 Tested Feed-forward loop on LRF2 during last downtime. Was able to adjust parameters for the gain of the tube and the time constant of the accelerating cavity (~30 us) Was able to accurately predict gradient within about 25% over the entire range Next step will be to test the learning algorithm, with appropriate gain clamping, and waveform advance, to see if flat gradient response is possible If successful, the following test will be to compensate for beam loading and check learning response It may turn on that beam is not stable without real-time or analog feedback, which will be visited if this is an issue – LRF2 is not a sensitive to pulse to pulse variations as LRF1, so it may be a good place for testing The goal is a final installation where the interlock system could be fully integrated into the modulator controls, resulting in the ability to run the system over multiple days, checking the long term stability

16. Voltage Command to Modulator - Red Gradient Reference (Desired) - Green Measured Gradient Waveform - Blue

17. Project Timeline Finish control card development and have final boards laid, ordered, and built (2 months) Finish assembly of Marx cells with the modifications learned from corona testing (3 months) Finish up design of 28 cell support structure and fabricate support structure and backplane (3 months) Continue work on testing learning algorithms on actual RF system until system can run without user interaction Test 28 cell version into dummy load (3-4 months) Build 54 cell version using what is learned in the 28 cell building and testing (6 months) Test 54 cell version into dummy load, followed by testing in actual RF system, using the code developed by testing on present tube modulator (6-7 months)