1. 1 H.Hübner et al. MAM 2006 Grenoble Infineon Micro Contacts with Sub-30µm Pitch for 3D Chip-on-Chip Integration MAM 2006, Grenoble, March 2006 Holger Hübner, Sabine Penka Markus Eigner, Wolfgang Gruber, Markus Nobis, Günter Kristen, Manfred Schneegans (Munich) Bernd Barchmann, Stephan Janka (Regensburg) Infineon Technologies AG Germany

2. 2 H.Hübner et al. MAM 2006 Grenoble Historical Background Outline

3. 3 H.Hübner et al. MAM 2006 Grenoble Historical Background Due to the steady increase of information density and shrink of design rules in the silicon 1.the traditional DIL package had been replaced by surface mount technologies using solder bumps (Ball Grid Arrays – BGA). 2.and also the first level wire bonds inside the package will be replaced by solder bumps (FBGA  Fine Pitch Micro Bumps)

4. 4 H.Hübner et al. MAM 2006 Grenoble Steadily Shrinking Dimensions of BGAs Micro bumps Chip-to-Chip Lead free BGA Chip-to Board PbSn Chip–to–substr. interconnect future? Chip–to–chip interconnect 60/12030/6015/30120 / 240 Package–to–board interconnects  200µm / pitch 500 µm today

5. 5 H.Hübner et al. MAM 2006 Grenoble Problems with Shrinking Dimensions  Decreasing compliance of the solder bump  Increasing growth velocity and influence of intermetallic phases during solder reflow - especially for lead free solders  Complicated architecture of the metallization (e.g. Cu – Ni/Au – SnAg – Ni – Cu)  A mix of multiple phases in the solder bump (electro migration driven)  Consumption of diffusion barrier during (high temperature) operation  Risc of erosion of the under-bump metallization

6. 6 H.Hübner et al. MAM 2006 Grenoble Argumentation for a New Technology (1)Compliance is only given (and needed) for chip-to-board interconnects (2)We focus on chip-to-chip interconnects (3)For chip-to-chip connections bumps must be low-scale and high density (4)If the influence of the intermetallics grows, why not build bumps completely out of intermetallics ? (5)Our new interconnect technology replaces the soft soldering by a soldering process called Solid-Liquid-InterDiffusion (SOLID)

7. 7 H.Hübner et al. MAM 2006 Grenoble Theory and Basics Outline

8. 8 H.Hübner et al. MAM 2006 Grenoble T ML liquid solid high melting phase solid soldering T T 2 1 MxLyMxLy Sn melts at the soldering temperature (231°C) Sn and Cu react to Inter Metallic Compounds (IMCs)  The melting point raises by several 100°C to T 2 and  The joint solidifies isothermally at the processing temperature Cu - Sn (3µm) - Cu SnCu Cu 3 Sn (  ) Cu 6 Sn 5 (  ) Metallurgical Basics of the SOLID Technology

9. 9 H.Hübner et al. MAM 2006 Grenoble B A   Sn Cu Kinetic of Phase Growth Diffusion paths A - via grain boundaries into the liquid solder B - through the  - phases C - via the  - phases (less important) Kinetics Initially very rapid Cu-diffusion and growth of  -phases via A (convection enhanced material transport within the liquid Sn) At the same time the  -phases grow laminar impeding more and more the phase growth (solid state diffusion via C) After Sn is consumed completely, the  -phase will be transformed to  -phase (solid state diffusion) C

10. 10 H.Hübner et al. MAM 2006 Grenoble Kinetic of Phase Growth *  A 3 µm gap solidifies within a few ten seconds  The ε-phase needs 15 - 20 min for the transformation of a 3 µm layer S. Bader MPI für Metallforschung Stuttgart, 1990  

11. 11 H.Hübner et al. MAM 2006 Grenoble Comparison of BGA vs SOLID Outline

12. 12 H.Hübner et al. MAM 2006 Grenoble Comparison of Solder Processes BGA - Solder bumpSOLID interface diffusion barrier Sn Cu Cu 3 Sn  Large solder volumen  Phase growth is controlled by -diffusion barrier (Ni/Au) and -low temperature budget  Solidification by cooling  Very thin solder layer -No barrier -Simple metallurgy  Sn is completely consumed  Solidification isothermally Sn Cu

13. 13 H.Hübner et al. MAM 2006 Grenoble Comparison of Solder Processes FBGA Metallization and solder apply SOLID Metallization and solder apply Pick & place (no flux) Soldering 1 st step 2 nd step 3 rd step 4 th step Reflow Pick & place (flux) Soldering

14. 14 H.Hübner et al. MAM 2006 Grenoble Comparison of Processes reflow defines shape of the balls before pick & place  All pads must be the same size  All pads must be the same shape  Larger spacing between balls, because balls expand  Complicated metallurgy (barrier, multiple IMCs)  Phase growth not finished  High homologous temperature BGASOLID reflow and soldering in a single step after pick & place  Different sizes possible  Different shapes possible  Smaller spacing (only limited by the bonder alignment)  Only two metals involved (barrier free, one IMC)  Thermodynamical stable  Low homologuos temperature Same processing for solder apply, but

15. 15 H.Hübner et al. MAM 2006 Grenoble Geometrical Comparison of BGA vs S OLID Soft solder bumps SOLID contacts  15µm / pitch 30 µm (limited by the bonder alignment accuracy) 7,5/15 Micro bumpsBGA Transition from soft solder to Inter Metallic Compounds (IMC) 60/12030/6015/30120 / 240  200µm / pitch 500 µm

16. 16 H.Hübner et al. MAM 2006 Grenoble SOLID-Face-to-Face Stack Top chip Cu and Sn coating Bottom chip Cu coating, bond pads No underfill Inter chip vias 15 x 15 µm² 5 µm vias to LM Redistribution Insulation trenches 15 µm Passive area heat spreader External IOs standard wire bonds

17. 17 H.Hübner et al. MAM 2006 Grenoble Benefits of the Planar Metal Interface  One single step for electrical and mechanical contact  Additional wiring layer  Very flat design  Electrical shield / base plane  Excellent heat conduction  Mechanical reinforcement of the point contacts  The top chip does not need an Al layer  No space consumption by testpads (Testpads can be designed within the passive area)  Top chip thinning after soldering  Modular process for multi-tier stacking (Si thru holes)

18. 18 H.Hübner et al. MAM 2006 Grenoble Process Flow Outline

19. 19 H.Hübner et al. MAM 2006 Grenoble Metallization (Testing) Top wafer thinning Singulation Pick, flip and place Soldering Bond process Chip to Wafer Wafer processes Initial state Opened passivation Vias Ø 5 µm, Al or Cu Sputtering TiW barrier 50nm Cu seedlayer 100nm Litho Insulation trenches Plating module Cu 5µm Top wafer only: Sn 3µm Resist strip Wet etch seedlayer and barrier CuSn Resist Oxide c-Si AlSiCu Cu Sn TiW Cu seed IMOX c-Si LM M1

20. 20 H.Hübner et al. MAM 2006 Grenoble Pick & Place 1 st Step – Sticking the chips on wafer Application of a liquid sticking agent by a jet dispenser The hard contact with the cold wafer freezes the sticking agent w/o time delay parallizes the chips (tilt adjustment) T = 70°C T = 25°C Solidification by cool down Demands on the sticking agent (bibenzyl): Melting point 50 - 60°C High vapour pressure (evaporation in vacuum) Inert, non corrosive, non hygroscopic No residues

21. 21 H.Hübner et al. MAM 2006 Grenoble 2 nd Step – Soldering of the populated wafer Demands on the soldering process  Evaporation of the sticking agent  Reduction of the Cu- und Sn-surfaces  Complete transformation of Sn to η-phase  No lateral shift of the chips during heating (horizontal placement)  No contamination of the surface (residue-free flux) Soldering Process parameters: 1 min @ 260°C; vacuum or inert gas

22. 22 H.Hübner et al. MAM 2006 Grenoble 3 rd Step (optional) – Final transformation η- into ε-phase  Batch oven  Inert gas Alloying Process parameter: 20 min @ 300°C

23. 23 H.Hübner et al. MAM 2006 Grenoble Cost Comparison with FBGA Outline

24. 24 H.Hübner et al. MAM 2006 Grenoble Cost Comparison with FBGA Cost reduction potential comes from  Thinner metal layers  Additional redistribution layer given „for free“  No Al-layer in the top chip  No flux cleaning after soldering  No underfill required  Wafer metallization is similar to electro plated FBGA  Standard equipment for test, pick & place, soldering and inspection  Only one minor add-on: jet dispenser

25. 25 H.Hübner et al. MAM 2006 Grenoble Experimental Results Outline

26. 26 H.Hübner et al. MAM 2006 Grenoble Experimental Results 30 µm Standard contact with &15 µm Pitch 30 µm Via to last metal  5 µm Demonstrator for 20 µm pitch

27. 27 H.Hübner et al. MAM 2006 Grenoble Experimental Results  Standars contacts (defined by bonder alignment): 15 x 15 µm², 5 x 5 µm² vias to last metal  10 µm pads with 20 µm pitch demonstrated  5 µm crossed lines have successfully been bonded  No influence of particles seen (class 10000 CR)  Thickness of the top chips: 80 µm, typically 125 µm  Shear strength of the bond: >120 N @ 25 mm² chip size  Measured contact resistance: 5 m  for a standard contact  Worst case simulation of stray capacities: 34 – 40 fF (w/o and w/ underfill)

28. 28 H.Hübner et al. MAM 2006 Grenoble Model lumped circuit Contact dimensions 15 x 15 µm² 40 fF (simulation) 5 m  (measured value) Conductor width 200 nm thickness 350 nm resistance 90 m  /  capacitance 250 aF/µm (standard Cu-wire in C9) Transit Frequency of a Single Contact R Contact C R C R Circuit line

29. 29 H.Hübner et al. MAM 2006 Grenoble Problem: Solder Squeeze Out Wrong design rule (w/o stiching) New design rule (stiched tin lines) Redistribution lines are prone to solder sqeeze out Theoretical background (surface tension) allows for exact calculation of design rules  Stiched tin volume prohibits solder squeeze-out X-ray image of a chip stack

30. 30 H.Hübner et al. MAM 2006 Grenoble Outline Reliability Results

31. 31 H.Hübner et al. MAM 2006 Grenoble Corrosion Behaviour of an Uprotected Solder Joint Reference probe FIB preparation of the chip edge no underfill After 96h @ 121°C, 100%  corrosion of the  -phase   -phase is inert  minor Cu-corrosion  Cu 

32. 32 H.Hübner et al. MAM 2006 Grenoble FIB preparation after 1000 h HTS (85°C, 85%) Top chip thinned by wet etch Corrosion Free Cavities No corrosion inside the stack cavity. Metallical seal ring Organical sealring (FF2200) protects  -phase

33. 33 H.Hübner et al. MAM 2006 Grenoble Temperature Cycles (TC) 73 chains of 500 standard contacts (15 x 15 µm², via 5 x 5 µm²) from LM to LM 1000 cycles -65…150°C, 1 h each cycles dR/R [%] Drift of 500 daisy chain

34. 34 H.Hübner et al. MAM 2006 Grenoble Contact After 500 T-Cycles -65 …150°C Void-free joint Alloying completed by a batch process Only two phases (Cu and Cu 3 Sn), no barrier No degradation, no re-cristallization Morphology remains unchanged in comparison to the reference probe, beside a growing cross linking during the first cycles Pitch 30µm 5 µm

35. 35 H.Hübner et al. MAM 2006 Grenoble High Temperature Storage (HTS) 140 chains of 500 standard contacts (15 x 15 µm², via 5 x 5 µm²) from LM to LM Two storage temperatures 175°C and 200°C dR/R [%]

36. 36 H.Hübner et al. MAM 2006 Grenoble Humidity Stress Results 15 µm space between solder line and base plane, length 2.5 mm, height 12 µm, with underfiller prestress UHAST AC Leakage current raises due to moisture uptake of the underfiller Resistance remains unchainged

37. 37 H.Hübner et al. MAM 2006 Grenoble Humidity Stress Results It will be a real concern for  small contact distances  for high pin counts  low power devices Possible counter measures:  Use of underfiller with less moisture uptake  Interface w/o underfiller  Seal ring The increase of the leakage current is a geometrical problem, when the insulation gap becomes more and more narrow. This is a technology-independant phenomenon and can also be seen at micro-bumped probes.

38. 38 H.Hübner et al. MAM 2006 Grenoble Despite a not yet optimized design, we succeeded in a self-aligning process with an alignment accuracy of  1 µm (Initial placement  10 µm) Self Alignment Diagonal cut through a contact chain (steps 1 µm each) Pitch 30µm

39. 39 H.Hübner et al. MAM 2006 Grenoble Thank you for your attention ! Many thanks to R. Tilgner / IFX for many valuable discussions !