1. CROWNE Current Ratio Outlier With Neighbor Estimator Sagar S. SabadeDuncan M. Walker Department of Computer Science Texas A&M University College Station, TX 77843-3112 http://ee.tamu.edu/~sagar Sagar S. SabadeDuncan M. Walker Department of Computer Science Texas A&M University College Station, TX 77843-3112 http://ee.tamu.edu/~sagar

2. Outline Introduction Variability in Current Ratios Use of Wafer Spatial Information – NCR metric Combining Multiple Parameters Experimental Results Conclusions

3. Introduction I DDQ test needs to survive in DSM era Many methods reported in literature – Goal: Reduce variance in “fault-free” I DDQ Current Ratio (CR) – Ratio of maximum to minimum I DDQ of a chip – Within-chip I DDQ variation similar for fault-free chip (magnitudes may differ) – Ease of implementation in production

4. CR Variation for Real Chips Can CR detect all defective chips? Smaller CR does not necessarily imply a fault-free chip – it may be a passive defect!

5. Why Use Spatial Information? Neighboring fault-free Chips have similar I DDQ For same vector

6. Neighbor Current Ratio (NCR) Take ratio of I DDQ of neighboring chips for same vector [details in our DFTS 02 paper] I DDQ Vector Number Chip 1 I DDQ readings Chip 2 I DDQ readings NCR (i) = I DDQ (chip1) (i) I DDQ (chip2) (i) N Nbrs, k vectors  N.k NCR values NCR = Max (NCR(i))

7. Combining CR and NCR Single metric alone not enough to catch defects CR looks “within-chip” variability NCR considers local neighborhood variation – Easy to detect passive defects with fewer vectors Gross outlier tail “CROWNE” chips

8. CR/NCR Combination Insights CR NCR Threshold CR Threshold 1 Region D Nominal CR,NCR Fault-free Chips/ Good chips in Bad neighborhood Region A Nominal CR Subtle active defects Spatial Outliers Region B CR, NCR Outliers Active defects Region C Outliers in Bad neighborhood Passive defects

9. CROWNE Chips Chips that are okay with CR alone – But are outliers when neighboring chips are used Are these chips – Defective?  should be rejected – Different?  okay to ship – Weak?  reliability concern

10. CR, NCR and Flush Delay XY projection

11. How does combination help us? CR NCRDelayResult Low SmallFast wafer region LargeResistive short/defect? Low High SmallA chip with passive defect Largein a good neighborhood High Low SmallA chip with active defect Largein a bad neighborhood High SmallA chip with active defect Largein a good neighborhood

12. Analysis of SEMATECH Data – 0.6  technology – 12521 chips – four test types – IDDQ, stuck-at, functional, delay – 195 IDDQ readings/chip, threshold 5  A – Screened all chips above 100  A, obvious outliers – Flush delay > 500 ns considered outlier – CR, NCR threshold decided from CDF CR threshold 5 NCR threshold 10

13. CR/NCR scatter plot for low CR More active More passive

14. CR/NCR scatter plots Some delay failures can be identified by NCR – No systematic pattern

15. Flush delay/NCR scatter plot Poor correlation between NCR and flush delay – NCR cannot screen delay failures well

16. Conclusion Low CR is deceptive – Can be passive defect; reliability hazard – Spatial information useful (e.g. NCR) Combination of CR/NCR has better outlier screening – NCR not suited for delay failures – Additional screen needed More data analysis needed to validate claims

17. Vector Relationship for CR/NCR Do the same vectors that give CR (max current) also cause highest NCR? – Total 195 vectors, which yields min and max I DDQ for CR? Which gives max NCR? CR = Max I DDQ / Min I DDQ “Intrinsic” fault-free current Defective current

18. Vector Pairs for CR and NCR 9 23 129 147 Min I DDQ Max I DDQ

19. Vector for NCR 129 174 147 Max I DDQ Max NCR