1. FCP130 Fermi CMS Pixel Test Chip
Davide Braga
on behalf of:
D. Christian, G. Deptuch, F. Fahim, J. Hoff, A. Shenai, M. Trimpl, T. Zimmerman

2. Outline FCP130 at a glance Motivations Synchronous ADC concept
Pixel architecture
Preamplifier
ADC comparator
Simulation results
Corners and mismatch
Pixel digital functionality
Data Readout
Layout
Top level assembly and design methodology
Summary and future developments
Fermilab FCP130
CMS Tracker Week, Jan2015

3. FCP130 at a glance GF 130nm 1.5V CMOS Pixel size: 100 x 30 μm2
ASIC size: 8.5 x 5.5 mm2 (48 x 160 pixel matrix) 4.8 x 4.8 mm2 active
Each pixels contains:
Charge-sensitive preamplifier with leakage current compensation
Synchronous 3bit flash ADC with 8 auto-zeroed comparators
(also a different design with a 3bit SAR ADC implemented in part of the matrix)
Thermometric and priority encoder
High-speed asynchronous data-driven readout
Expected analog power: 24 μW/pixel
ENC: Cdet=30fF
Submitted in September 2014, shipped last week.
Fermilab FCP130
CMS Tracker Week, Jan2015

4. Motivations Allow progress with sensor development
FRONT-END: validate design for Phase-II Pixel (RD53 specifications) with:
Synchronous front-end
Low-power unidirectional preamplifier and comparator
Novel leakage current compensation scheme
Novel comparator
BACK-END: demonstrate novel asynchronous, data-driven readout scheme developed at Fermilab (Conflux)
Parameter
RD53 Target Specification
Pixel area
2500 μm2
Noise fF
Sensor thickness
polarity
100 : 300 μm
electrons
Radiation dose
10 MGy
2E16 MeVneq/cm2
Minimum Threshold
1000 e-
Power per channel
< 25 μW
Fermilab FCP130
CMS Tracker Week, Jan2015

5. Synchronous ADC concept
Fast shaping may worsen S/N due to ballistic deficit
Conversion begins as soon as charge starts being integrated and continues until signal reaches maximum or conversion time is over.
 no dead time for conversion.
Fermilab FCP130
CMS Tracker Week, Jan2015

6. Configuration register
CompOutB<6>
Active resistor
Leakage Current Compensation
Core
Amplifier
Source
Follower
Vth0
Vth1
Vth2
Vth3
Vth4
Vth5
Vth6
Vth7
ComparatorB
Comparator
CompRst & CompRstB
Cfb =11.6fF
Ctest =1.6fF
IN_TEST
PIX_ANA
Vth0-7
From DIGITAL PIXEL
Preamplifier Bias (GLOBAL SIGNALS)
Comparator Bias
ILEAK
IBIAS2A
IBIAS1A
VBIAS
ISET2
ISET1
To DIGITAL
section
ANA_TEST
(GLOBAL SIGNALS)
analogDisable
vssa!
CompOutB<1>
CompOutB<2>
CompOutB<3>
CompOutB<4>
CompOutB<5>
CompOutB<7>
Hit In
(Bump bond
PAD)
Pixel architecture
analog section
digital section
Hit Processor
Thermometric Encoder
Priority Encoder
Configuration register
compOutB<7:1>
Hit
(from
previous pixel)
configIn
configClk
configOut (to next pixel)
ADC<2:0>
ADR<5:0>
Set
Kill
readRequest
selectPixelB
BXClk
analogDisable
readStrobe
digReset
Synchronous front-end + ADC
No ballistic deficit due to lack of shaping amplifier
3bit flash ADC per pixel: increased noise immunity
CDS removes offsets and increases pileup immunity
Fermilab FCP130
CMS Tracker Week, Jan2015

7. Preamplifier Electron readout
Linearity: 1.5% for an input signal in 0.125fC – 4fC range
Power Consumption: 12µW (8µA x 1.5V)
Regulated cascode design
Feedback capacitor: 11.6fF
Active transistor resistive feedback
Large signals behaves as a constant current source
Small signals Rf = 1/gm
Leakage current compensation up to 5nA
AC coupled to comparators
(must drive 8x11.6fF=92fF)
Fermilab FCP130
CMS Tracker Week, Jan2015

8. ADC Comparator Compact, single-ended architecture
Correlated double sampling:
Auto-zeroed
Increased pileup immunity
Signal filtering
No need for trimming DACs
12.5ns reset phase; 12.5ns active comparison
Low-power, fast, insensitive to corners
Additional gain and positive regeneration in 2nd stage.
BXclk must be well controlled across a large chip
1.5µW/comparator
Out
low Vt
Clamp to maintain constant Idd
Low capacitance to minimize threshold transients
Gain with positive regeneration
ΔVth
ΔVsig In
Vth
Gnd
Switches use BXclk for reset/compare
Fermilab FCP130
CMS Tracker Week, Jan2015

9. Simulation results Response to a 12500e- input charge
Transient noise simulation (Qin=1000e-)
Fermilab FCP130
CMS Tracker Week, Jan2015

10. Corners and Mismatch
Pixel relatively insensitive to process variations: mismatch across chip responsible for response variation
Detector
Capacitance
[fF]
Preamp
output noise
[eRMS]
Noise
after CDS
Comparator
phase noise
[psRMS] 15 38 35
427 30 43 42
486 45 48 47
496 60 53 52
534
100 64
616
MonteCarlo simulation of comparator switching time for Qin=800e-, injected at 12.5ns: the main contribution is due to mismatch.
Noise simulations results
Fermilab FCP130
CMS Tracker Week, Jan2015

11. Pixel: digital functionality
Hit Processor
Thermometric Encoder
Priority Encoder
Configuration register
compOutB<7:1>
Hit
(from
previous pixel)
configIn
configClk
configOut (to next pixel)
ADC<2:0>
ADR<5:0>
Set
Kill
readRequest
selectPixelB
BXClk
analogDisable
readStrobe
digReset
ADC thermometric encoder
Configuration register: 2bit to set or disable pixel
Hit Processor: latches Hit or Set to generate readRequest to trigger the Priority Encoder
Priority Encoder: based on Fisher Tree, generates a 6b pixel address for the column. The end of column logic issues a selectPixel signal to initiate readout.
Fermilab FCP130
CMS Tracker Week, Jan2015

12. Data Readout Conflux: 4-phase asynchronous handshake protocol
High-speed
Data-driven
Does not need high speed clocks or any global control signal
Allows for daisy-chaining of data
(patent pending)
Data packet:
3b chip ID or timestamp
+ 6b super-column address
+ 8b pixel address
+ 3b signal amplitude
20b/hit
Optional serial output mode

13. Layout … super-column analog digital 30μm 20μm 10μm 120μm 1 3 2 4
comparator 48 47
flash ADC 46
100μm 45
4800 μm … 3
Transistors placed in deep-nwell, double-pixel layout ADDA 2
preamplifier 1
super-column
analog
digital

14. Top level assembly and Design methodology
Single Pixel:
Analog: Virtuoso Layout XL
generated abstract for Encounter and Verilog model with timing information from analog simulation (for top level simulation)
Digital: custom compact cells
VSR (space-based router, fast, no significant delay within pixel)
Super Column:
Encounter (timing-driven)
Created timing libraries from parasitic extraction for different corners and temperature settings
Signoff accuracy
Top Level:
Top level parasitic extraction and simulation
Timing-driven distribution of clock and read strobe, buffer tree synthesis for all global reset signals
 BXclock variation across chip <2ns
test structure
8500 μm
4800 μm
Test features:
Spy analog and digital signals available on EAST pads
Single pixel with preamplifier output and all comparators’ outputs available for debugging
4 separate power supplies to monitor current of individual blocks
Size compatible with bonding of baby sensors
end-of-column logic

15. Summary and Future Developments
A 48x160 small cell pixel demonstrator chip has been developed which employs synchronous ADC and a novel low-power comparator circuit and leakage current compensation.
FCP130 is also a demonstrator for a novel data-driven asynchronous high-speed readout.
Translation to 65nm being explored in collaboration with INFN
Initial results show 40% reduction in analog power consumption, making the flash ADC scheme even more appealing.
The chips should be delivered within days, silicon sensors developed at Purdue U. ready to be bump-bonded.
Fermilab FCP130
CMS Tracker Week, Jan2015

16. Backup: comparator schematic
Fermilab FCP130
CMS Tracker Week, Jan2015