2. FPGA VHDL eP32 Design 2012 FIG Taiwan Conference February 17, 2012 Chen-Hanson Ting

3. Summary Brevia FPGA Development Kit Architecture of eP32 Implementing eP32 Memory and IO Brevia Board and LatticeXP2 ispLEVEL and Diamond IDE Demomnstration

4. Brevia FPGA Development Kit Lattice XP2 Brevia Kit is a complete FPGA development system for $49. The FPGA chip on Lattice Brevia Kit let us design and implement your own microcontrollers. A 32-bit Forth microcontroller eP32 is demonstrated here.

5. Brevia FPGA Development Kit For $49, you can design, build and test your own microcontroller. The on-board FPGA chip, LatticeXP5E, can host a complete 32-bit microcontroller system. eP32 is implemented in VHDL, with Forth operating system and programming language.

6. LatticeXP2 Brevia Kit

7. Brevia Board LatticeXP2-5E 6TN144C FPGA 2-Mbit SPI flash memory 128K by 8-bit SRAM 8 switches/pushbuttons 8 status LEDs USB download and serial cable

8. LatticeXP2-5E 6TN144C 5K LUT4 Logic cells 166K Bits Embedded block memory 10K Bits Distributed memory 3 DSP Blocks 12 18x18 Multipliers 144 Pin TQFP Package

9. The Most Satisfying FPGA I have tried FPGA ’ s from all Big 4: Market Share2009 SalesFPGA Xilinx50%$1,825MVirtex, Spartan Altera30%$360MStratix, Cyclone Lattice10%$194MECP3, XP2 Actel6%$190MIGLOO, ProASI Lattice has the most satisfying FPGA, a single chip SOC solution Lattice has the cheapest development board. $49 Lattice provides free development software.

10. Brevia Design Tools ispLEVEL or DIAMOND IDE Synthesis: Synplify Simulation: Active-HDL from Aldec Layout: Design Planner Flash Programming: ispVMR Tracing and Debugging: ispReveal

11. Architecture of eP32 A 32-bit CPU (Central Processing Unit) Two stacks to support Forth Language: Return stack for nested return addresses Parameter stack to pass parameters among nested subroutines Minimal instruction set Single clock cycle execution time Optimized subroutine call and return

12. Block Diagram of eP32 CPU

13. ALU and Data Processing Unit

14. Program and Data Memory Unit

15. Return Address Processing Unit

16. Instruction Execution Unit

17. Instruction Execution Timing

18. Instruction Set of eP32 CPU Minimum Instruction Set Computer (MISC) Only 27 Instructions, expandable to 64 instructions 4 Types of instructions: Program transfer instructions Memory access instructions ALU instructions Register and stack instructions

19. Program Transfer Instructions BRA Branch always RET Return from subroutine BZ Branch on zero BC Branch on carry CALL Call subroutine NEXT Loop until R is 0

20. Memory Access Instructions LDXLoad from memory LDXP Load from memory and increment X register LDI Load immediate value STXStore to memory STXP Store to memory and increment X register

21. ALU Instructions ADDAdd S to T ANDAND S to T XORXOR S to T COMOne ’ s Complement of T SHRShift T to right SHLShift T to left RR8Rotate T right by 8 bits MULMultiplication step DIVDivision step

22. Register and Stack Instructions DUPDuplicate T to S DROPPop S to T PUSHPush T to R POPPop R to T OVERDuplicate S over T TXLoad X to T XTStore T to X NOPNo operation

23. Implementing eP32 eP32_chip.vhd, top level design eP32q_tb.vhd, test bench Modules eP32.vhd, CPU core Ram_memory.vhd, 4096x32 auto- initialized RAM memory Uart.vhd, 115200 baud Gpio.vhd, 16 bit bidirectional

24. Synthesizing eP32 Ep32.vhd, uart.vhd and gpio.vhd are synthesized without modification Ram_memory.vhd must be constructed to use RAM_Q modules in LatticeXP2-5E FPGA chip. Ep32_chip.vhd instantiates new ram_memory.vhd with all other modules

26. Simulating eP32 Active-HDL simulation tools are supplied by Aldec. ispLEVEL needs a test bench module for functional simulation of eP32 chip: ep32q_tb.vhd DIMOND simulates ep32_chip directly.

28. Memory and IO Design Planner to assign following signals to physical pins: External reset External master clock Interrupts GPIO to LED and switches UART transmit UART receiver

30. Programming XP25E FPGA Connect USB cable to PC. Invoke Programmer to download ep32_xp2.jed file. eP32 eForth boots up and sends sign- on message to HyperTerminal console.

32. Demonstration Boot up eForth on eP32. Universal greeting “ Hello, World! ”. Turn LED ’ s on and off. Read switches and push buttons.