1. High-level Synthesis and System Synthesis SOURCES- Mark Manwaring Kia Bazargan Giovanni De Micheli Gupta Youn-Long Lin Camposano, J. Hofstede, Knapp, MacMillen Lin

2. Why the level of automation must go up and up?

3. What Went Wrong with early approaches to design automation ? 1.Too much emphasis on incremental work on algorithms and point tools 2.Unrealistic assumption on component capability, architectures, timing, etc 3.Lack of quality-measurement from the low level 4.Too many promises on fully automated system (silicon compiler??)

4. Example of a Silicon Compiler System Initial specification

5. Benchmarks for a silicon compiler

6. VLSI Design Tools Design Capturing/Entry Analysis and Characterization Synthesis/Optimization Physical (Floor planning, Placement, Routing) Logic (FSM, Retiming, Sizing, DFT) High Level(RTL, Behavioral) Management

7. Design Methodology Progress Capture and Simulate Describe and SynthesizeSpecify and ???

8. Productivity Re-Targetability Correctness Why Synthesis? Unsynthesizability Performance Loss Inertial Why not Synthesis?

9. StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan Y-Chart Dan D Gajski

10. StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan Layout Synthesis

11. StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan Logic Synthesis

12. StructuralBehavioral Physical X’tor Gate RTL Block Boolean FSM Algorithm GDSII Placement Floorplan High-Level Synthesis

13. Target Architectures Bus-based Multiplexer-based Register file Pipelined RISC, VLIW Interface Protocol

14. Goal of synthesis for future systems From Behavioral specification at ‘System Level’ (Algorithms) To Structural implementation at ‘Register Transfer Level’ of Data path (ALU’s, REG’s, MUX’s) and Controller Generally restricted to a single process Generally data path is optimized; controller is by-product

15. Levels of Abstraction In Camposano Behavioral Register-Transfer (RTL) Logic Our Abstraction levels System Register Logic

16. Abstraction levels System High-level Logic Physical Synthesis step LevelBehaviorStructure

17. Intermediate Representation ** + Control Flow Graph Data Flow Graph

22. What are possible levels of synthesis? What are possible styles? How to automate big tasks?

24. Layout Synthesis

25. Compass Placement & Routing ( 0.6µm gate array )

26. Layout Level

27. Logic Synthesis

28. Reminder about blocks and connections in data path

29. Variants of simple FSMD architectures control Controlling /activation pulses Data Path Controlling /activation pulses Status signals controlData Path

30. Variants of simple FSMD architectures control Controlling /activation pulses Data Path Status signals Instructions

31. FSM with Data Path (FSMD) FSM Data Path FSM Data Path FSM Data Path Interactive FSMDs

32. Details of control signals controls: Reg_EOEnable Output Reg_EIEnable Input RegFile_EIRegFile_SI Register; a) RTL level b) with control signal details

33. Control of register files control signals: RegFile_EO1 RegFile_SO1 RegFile_EO2 RegFile_SO2 RegFile_EI RegFile_SI Register; a) RTL level b) with control signal details

34. The role of tri-state signals Tri-state signals in buses instead of multiplexing Scheduling and allocation problems are similar

35. Multiplexing

36. Communication with a memory External data-bus External address-bus Internal bus

37. Pipeline Design Issues Pipelined processor design Pipeline is an implementation issue. A behavioral representation should not specify the pipeline. Most processor instruction sets are conceived with an implementation in mind. The behavior is defined to fit an implementation model.

38. Semantics of variables Variables are implemented in hardware by: Registers. Wires. The hardware can store information or not. Cases: Combinational circuits. Sequential circuits.

39. Semantics of variables Combinational circuits. Multiple-assignment to a variable. Conflict resolution. Oring. Last assignment. Semantics of variables

40. Sequential circuits. Multiple-assignment to a variable. Variable retains its value until reassigned. Problem: Variable propagation and observability. Semantics of variables

41. Example Multiple reassignments: x= 0 ; x = 1 ; x = 0 ; Interpretations: Each assignment takes a cycle. --> pulse. x assumes value 0. x assumes value 0 after a short glitch. Semantics of variables

42. Timing semantics Most procedural HDLs specify a partial order among operations. What is the timing of an operation? A posteriori model: Delay annotation. A priori model: Timing constraints. Synthesis policies. Semantics of variables

43. Timing semantics (event-driven semantics) Digital synchronous implementation. An operation is triggered by some event: If the inputs to an operation change --> the operation is re-evaluated. Used by simulators for efficiency reasons.

44. Synthesis policy for VHDL and Verilog Operations are synchronized to a clock by using a wait (or @) command. Wait and @ statements delimit clock boundaries. Clock is a parameter of the model: model is updated at each clock cycle.

45. Verilog example behavior of sequential logic circuit module DIFFEQ (x, y, u, dx, a, clock, start); input [7:0] a, dx; inout [7:0] x, y, u; input clock, start; reg [7:0] xl, ul, yl; always begin begin wait ( start); while ( x < a ) begin xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + (u * dx); @(posedge clock); x = xl; u = ul ; y = yl; end endmodule

46. Abstract models Models based on graphs. Useful for: Machine-level processing. Reasoning about properties. Derived from language models by compilation.

47. Abstract models Examples Netlists: Structural views. Logic networks Mixed structural/behavioral views. State diagrams Behavioral views of sequential logic models. Dataflow and sequencing graphs. Abstraction of behavioral models.

48. Data flow graphs Behavioral views of architectural models. Useful to represent data-paths. Graph: Vertices = operations. Edges = dependencies.

49. Dataflow graph Example xl = x + dx ul = u - (3 * x * u * dx) - (3 * y * dx) yl = y + u * dx c = xl < a

50. Example of Data Flow Graph continued xl = x + dx ul = u - (3 * x * u * dx) - (3 * y * dx) yl = y + u * dx c = xl < a

51. Sequencing graphs Behavioral views of architectural models. Useful to represent data-path and control. Extended data flow graphs: Operation serialization. Hierarchy. Control- flow commands: branching and iteratio n. Polar: source and sin k.

52. Example of sequencing graph

53. Example of Hierarchy

54. Example of branching

55. Example of iteration diffeq { read (x; y; u; dx; a); repeat { xl = x +dx; ul = u - (3 * x * u* dx) - (3 * y * dx); yl = y +u dx; c = x < a; x = xl; u = ul; y = yl; } until ( c ) ; write (y); }

56. Example of iteration

57. Semantics of sequencing graphs Marking of vertices: Waiting for execution. Executing. Have completed execution. Execution semantics: An operation can be fired as soon as all its immediate predecessors have completed execution

58. Vertex attributes Area cost. Delay cost: Propagation delay. Execution delay. Data-dependent execution delays: Bounded (e.g. branching). Unbounded (e.g. iteration, synchronization).

59. Properties of sequencing graphs Computed by visiting hierarchy bottom-up. Area estimate Area estimate: Sum of the area attributes of all vertices. Worst-case - no sharing. Delay estimate Delay estimate (latency): Bounded-latency graphs. Length of longest path.

60. Summary on specification models Hardware synthesis requires specialized language support. VHDL and Verilog HDL are mainly used today: Similar features. Simulation-oriented. Synthesis from programming languages is also possible. Hardware and software models of computation are different. Appropriate hardware semantics need to be associated with programming languages. Abstract models: Capture essential information. Derivable from HDL models. Useful to prove properties.

61. Control Design

64. Control 1 Control of Registers Functional units Multiplexers and 3-state drivers Memory Control design

65. Simple micro-programmed controller MUX INCR Program counter Microcode ROM Mode registers Jump address Control signals from ROM or data path Control lines

66. Control 2 1.To avoid false combinational cycles, either the inputs or the outputs of the controller are registered. 2.Note the one cycle delay between a condition and the resulting reaction in the controller. 3.Controller can even be pipelined, which can remove the controller from the critical path, but increases the delay for the conditions. Control design issues

67. Overview of Hardware Synthesis converts the program text file into strings of tokens. Tokens can be specified by regular expressions. In the UNIX world, the “lex” tools are popular for this. The syntax of a programming language is specified by a grammar. (A grammar defines the order and types of tokens.) This analysis organized streams of tokens into an abstract syntax tree.

68. Overview of Hardware Synthesis analyze the semantics, or meanings, of the program. Generate a symbol table. Check for uniqueness of symbols and information about them. determine the order and organization of operations