1. מבנה מחשב – מבוא למחשבים ספרתיים Encoders, Decoders & Shifters תרגול מספר 5

2. Encoder F Specification: Functionality:

3. Proof of Correctness By induction. Base:

4. Proof of Correctness Induction assumption: Encoder F (n-1) is correct Induction step: Prove that if the design is correct for k-1, it is also correct for k.

5. Proof of Correctness Induction step: We need to examine the output closer Since weight(x)=1, one of the components must be all zeros.

6. Induction step - continued There is at most one i for which x[i] = 1 First case:

7. Induction step continued Second case:

8. Induction Step continued Third case:

9. Induction Step continued Calculating F

10. Induction Conclusion If Encoder F (k-1) is correct then Encoder F (k) is correct. Since Encoder F (1) is correct (base), it follows that Encoder F (n) is correct for all n.

11. Cost of Encoder F

12. Delay of Encoder F

13. Cost of Decoder Each of the 2 n output gates is fed by a different non-trivial gate, therefore the cost must be at least that much.

14. Cost of Encoder * There are 2 n inputs which are fed into non- trivial gates. If the fan-in is bounded, then there must be an order of that size of input gates Another way to view it: each output bit has a cone of exactly 2 n-1. Why?

15. Delay of Decoder & Encoder * Decoder - Using the theorem shown in class: Encoder - Using the same method:

16. Barrel Shifter

17. Functionality Preservation If we swap the order of the blocks with their inputs will the functionality be preserved? If we swap the order of the blocks without swapping their inputs will the functionality be preserved?

18. Asymptotic Optimality of Delay The delay of the circuit is log(n) How can we prove optimality? We can view the circuit as having n+log(n) inputs. Each output bit is in a certain situation affected by every input bit. Therefore the cone of every output bit is n+log(n) This results in a delay that is O(log(n)).