1. Computation Energy Randy Huang Sep 29, 1998

2. Outline n Why do we care about energy/power n Components of power consumption n Measurements of power consumption n Reduction of power consumption n Summary

3. Introduction n What is computation energy? n Why do we care about energy? –PGAs excel in multi-media applications that are needed in hand-held battery- operated devices –easy to build devices that burn hundreds of watts if not careful

4. Energy and Power n Energy = Power / Toggle Frequency n P avg = P dyn + P sc + P leak + P static n P dyn is about 90% of power consumption

5. Dynamic Power Consumption n P = C x V dd x V swing x f x activity factor n Look at graph of inverter n Look at typical values

6. Power Measurement n Get a real chip and measure it n Get a circuit design and simulate it n Build a model Question: why would you choose one method over another?

7. Xilinx 4003 Measurements n Look at table of Xilinx measurements n Compared to the typical value we calculated earlier

8. Why is the number so bad? n Review sources of power consumption n Look at the pie chart again

9. Why is interconnect so bad? Look at a picture of heavily loaded FPGA interconnect with series connection of switches explain series of resistance effect plus transistor hanging off the interconnect, that it becomes highly resistive and capacitive

10. Circuit Simulation n Need a circuit representation n Use SPICE n Use random inputs?

11. Build a model n Cautionary words from Randy n Power factor approximation method from UC San Diego n Dual bit type model from UC Berkeley

12. Power Factor Approximation P avg =  Gf  =

13. Results of Power Approximation Look at the graph of   

14. Dual Bit Type Model n Look at bits of dynamic range graph

15. Dual Bit Type Model n Look at the bit correlation graph

16. Results of Dual Bit Type Model n Look at subtracter graph

17. Power Consumption Reduction n Review dynamic power consumption n Hierarchy of low power technique –algorithm –architecture –logic/cad –circuit –device

18. Algorithm Level Technique n Flexible, greatest amount of leverage n Parallelization n Correlation

19. Architecture Level Technique n Pipelining n Gated clock n Reducing the number of busses and switches n Reducing fanout? n Size of CLB

20. Logic Level Technique n Mapping n Locality n Constant propagation

21. Circuit Level Technique n Circuit family n Reduce swing on the buses

22. Device Level Technique n Great effect on C, V supply and everything else

23. Summary n Why do we care about energy/power n Components of power consumption n Measurements of power consumption n Reduction of power consumption n Question: Do PGAs offer better computation energy efficiency than general purpose processor?