1. Trace-Based Framework for Concurrent Development of Process and FPGA Architecture Considering Process Variation and Reliability 1 Lerong Cheng, 1 Yan Lin, 1 Lei He, and 2 Yu Cao 1 EE Department, UCLA 2 EE Department, ASU Address comments to lhe@ee.ucla.edulhe@ee.ucla.edu

2. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

3. Review of Previous Work Device and architecture co-optimization  Power and delay [Cheng DAC’05]  Process variation [Wong ICCAD’05]  Soft error rate [Lin, ICCAD’07]

4. Limitation of Ptrace Ptrace requires a stable SPICE model which is able to consider all process corners  SPICE model is not available at the early stage of process development Circuit simulation for all process corners is time consuming  The accuracy of circuit simulation is not needed for quick architecture evaluation Does not handle realistic variation  Non-Gaussian variation sources  Spatial correlation Does not handle device aging

5. Extended Ptrace (Ptrace2) Trace Circuit Element Statistics Critical Path Structure Switching Activity Process parameters Chip Level Leakage Power Dynamic Power Delay Reliability Soft Error Rate Device Aging Process Variation Power Distribution Delay Distribution InputOutput PTrace2 Reliability Chip Level Power and Delay Estimation Variation Analysis Circuit Level Power and Delay Estimation Transistor Electrical Characteristics

6. Early-Stage Circuit Modeling ITRS MASTAR4 model [ITRS MASTAR4 2005] Inputs: Lgate Tox Nbulk Xjext W Racc T Vdd Outputs: Ioff Ion Igon Igoff Cg Cdiff

7. Extended Ptrace Trace Circuit Element Statistics Critical Path Structure Switching Activity Process parameters Chip Level Leakage Power Dynamic Power Delay Reliability Soft Error Rate Device Aging Process Variation Power Distribution Delay Distribution InputOutput PTrace2 Reliability Chip Level Power and Delay Estimation Variation Analysis Circuit Level Power and Delay Estimation Transistor Electrical Characteristics

8. Circuit Level and Chip Level Power and Delay Circuit level power and delay  Inverter  Pass transistor driven by an inverter Chip level power and delay  Similar to the original Ptrace [Cheng DAC ’ 05, Wong ICCAD ’ 05]

9. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

10. Experimental Setting 20 MCNC benchmarks  Assume all 20 MCNC benchmarks are placed in the same chip ITRS high performance 32nm technology (HP32) Architecture  Cluster size N=6  LUT size K=7  Wire segment length W=4 Device  Vdd=1.0, 1.05, 1.1 V  L gate =31, 32, 33 nm Baseline ITRS HP32

11. Delay and Power Tradeoff 3.1X energy span and 1.3X delay span within search space

12. Power and Delay Optimization DevicePower (W) Delay (ns) Energy (nJ) ED (nJ·ns) HP321.193.901.8822.6 Min-ED0.774.553.5015.9(-29.4%) Device tuning reduces energy delay product by 29.4%

13. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

14. Experimental Setting Variation sources  Doping density N bulk 3 σ g =5% of nominal value, 3 σ r =3% of nominal value  Gate channel length L gate 3 σ g =0.8nm, 3 σ r =0.6nm Simulation  M=10,000 sample Monte Carlo simulation

15. Power and Delay Distribution

16. Power and Delay Variation Min-ED device setting significantly reduce leakage variation with a small increase of delay variation Device Leakage (mW)Delay (ns) µσµσ HP329423343.910.119 Min-ED34045 (-87%)4.550.159 (+34%)

17. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

18. NBTI and HCI Negative-bias-temperature-instability (NBTI) effect increases the threshold voltage of PMOS [Wang DAC’06] hot-carrier-injection (HCI) increases the threshold voltage of NMOS [Wang CICC’07] Inputs: Lgate Tox Nbulk Xjext W Racc T Vdd Outputs: ΔV th (NBTI) ΔV th (HCI)

19. V th Increase Caused by NBTI and HCI V th increase is the most significant in the first year Device burn-in can be applied to reduce the impact of device aging

20. Impact of Device Burn-in High performance device setting is more sensitive to device aging Device aging leads to 8.5% of delay degradation after 10 years Device burn-in reduce delay degradation from 8.5% to 5.5% after 10 years Device W/O Burn-inW/ Burn-in Current10 yearsCurrent10 years P (mW)D (ns)P (mW)D (ns)P (mW)D (ns)P (mW)D (ns) HP328543.90 640 (-25.1%) 4.23 (+8.5%) 7114.01 627 (-10.0%) 4.25 (+5.5%) Min-ED3284.55 311 (-5.2%) 4.64 (+2.0%) 3174.59 309 (-1.9%) 4.65 (+1.1%)

21. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

22. Permanent Soft Error Rate Single-event upset (SEU) due to cosmic rays or high energy particles may affect configuration SRAMs in FPGAs and result in permanent soft error Inputs: Lgate Tox Nbulk Xjext W Racc T Vdd Outputs: SER

23. SER under Different Device Setting SER for both device setting is similar DeviceSER (FIT) HP32362.45 Min-ED368.25 (+1.6%)

24. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

25. Impact of Device Aging on Power and Delay Variation Device aging significantly reduces leakage variation and slightly increase delay variation Device σ Leakage (W) σ Delay (ns) Current10 yearsCurrent10 years HP32334116 (-65.2%)0.1190.121 (+1.67%) Min-ED45.030.3(-32.7%)0.1590.159 (+0.16%)

26. Impact of Device Aging and Process Variation on SER Neither device aging nor process variation has significant impact on permanent SER Current10 yearsVariation SRAM SER (FIT)2.914E-5+0.3%-0.18% ~ +0.17%

27. Outline Introduction  Review of existing work  Process models Concurrent development of process and architecture  Power and delay  Process variation Concurrent development for reliability  Device aging  Permanent soft error rate (SER)  Interaction between process variation and reliability Conclusion

28. A trace-based framework has been developed to enable concurrent process and FPGA architecture co-development Device tuning achieves significant energy delay product reduction Applying device burn-in reduces delay degradation from 8.5% to 5.5% within 10 years Device aging significantly reduces leakage variation but has has almost neglegible impact on delay variation Neither device aging nor process variation has significant impact on permanent SER