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Implementing Digital Circuits Lecture L3.1
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Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family
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Discovery of the Electron -- 1898 J. J. Thomson Cathode Tube Cavendish Labs Electric Field -- “corpuscle”
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The Vacuum Tube
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The First Point-Contact Transistor 1947 Bell Labs Museum
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The First Junction Transistor 1951 Bell Labs Lab model M1752 Outside the Lab
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Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel
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Moore’s Law
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Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family
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Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates to arithmetic logic units Becoming obsolete with the development of programmable logic devices (PLDs)
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Transistor-Transistor Logic (TTL) Diode-Transistor Logic DTL Transistor-Transistor Logic (TTL) "Totem Pole" output
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TTL Chips
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TTL NAND, NOR, XOR
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TTL Multiple-input Gates
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Small-Scale Integrated (SSI) Circuits 1 to 10 gates NAND gate has 4 transistors
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Medium-Scale Integrated (MSI) Circuits 10-100 gates Adders Comparators Multiplexers Decoders
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Large-Scale Integrated (LSI) Circuits 100-1000 gates Arithmetic Logic Units
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Very-Large-Scale Integrated (VLSI) Circuits >1000 gates Microprocessors Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)
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Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family
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A Programmable Logic Device
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A = X & !X & Y & !Y = 0 & 0 = 0
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A Programmable Logic Device A = X & !X & Y & !Y = 0 & 0 = 0 Z = A # B = 0 # B = B
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Alternate PLD Representation
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Make PLD Connections for AND XY X!XY!Y A B Z 1 2 XX XXXX
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Make PLD Connections for OR XY X!XY!Y A B Z 1 2 X X
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Make PLD Connections for NAND XY X!XY!Y A B Z 1 2 X X
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Make PLD Connections for NOR XY X!XY!Y A B Z 1 2 XX XXXX
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Make PLD Connections for XNOR XY X!XY!Y A B Z 1 2 XX XX A B C 0 0 1 0 1 0 1 0 0 1 1 1
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Make PLD Connections for XOR XY X!XY!Y A B Z 1 2 XX XX A B C 0 0 0 0 1 1 1 0 1 1 1 0
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The GAL 16V8 1 2 3 4 5 6 7 9 1011 12 8 19 20 17 18 15 16 13 14 GND Vcc I/CLK II/O I I I I I I I I/OE I/O GAL 16V8
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Structure of the GAL 16V8 PLD
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GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A open B = 1 C = !A Polarity Pin
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Typical PLD Flip-Flops
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Structure of the GAL 16V8 PLD
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XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE 1149.1 JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1
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XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !
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XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288
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PLDT-3 Xilinx XC95108 CPLD 7 segment display Switches LEDs Buttons
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Xilinx 95108 6 function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs
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Architecture of the Xilinx XC95108 CPLD
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Each Xilinx 95108 macrocell contains a D flip-flop Controlled inverter
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Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x Note asynchronous reset y z
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Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family
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Block diagram of Xilinx Spartan-3 FPGA
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Each Spartan-3 CLB contains four CLB slices
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Left-hand Slice SLICEM
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Top of Left-hand Slice SLICEM
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16 x 1 SRAM Lookup Table
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Look Up Tables Capacity is limited by number of inputs, not complexity Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1... 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !
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Center of Left-hand Slice SLICEM
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Bottom of Left-hand Slice SLICEM
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Xilinx Spartan-3 FPGAs
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Block RAM
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Digital Clock Manager (DCM)
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Delay-Locked Loop (DLL)
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Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family
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Virtex FPGAs For info on Virtex 1000 boards, see http://www.zarx.info/
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Virtex-II FPGAs
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Virtex-II Pro FPGAs
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CPLDs vs. FPGAs
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Virtex-4 FPGAs
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