1. Winter-Spring 2001Codesign of Embedded Systems1 Introduction to HW/SW Co-Synthesis Algorithms Part of HW/SW Codesign of Embedded Systems Course (CE 40-226)

2. Winter-Spring 2001Codesign of Embedded Systems2 Topics Introduction Preliminaries Hardware/Software Partitioning Distributed System Co-Synthesis Conclusions

3. Winter-Spring 2001Codesign of Embedded Systems3 Introduction to HW/SW Co-Synthesis Algorithms Introduction

4. Winter-Spring 2001Codesign of Embedded Systems4 Introduction Implementing a system? Why use CPU? Easier implementation Easier (and cheaper) to change and debug Why use hardware modules? Meeting other constraints performance, power consumption, etc Found a CPU meeting all non-functional constraints? Yes! What could be better? Use the CPU. No! Design custom logic, or a combination of both

5. Winter-Spring 2001Codesign of Embedded Systems5 Introduction (cont’d) Why more than one CPU or custom logic? Why not use the fastest available CPU?

6. Winter-Spring 2001Codesign of Embedded Systems6 Introduction (cont’d) Reason 1: Exponential cost per CPU performance Figure: late-1996 retail prices of Pentium Processor Pentium processor prices Clock speed (MHz)

7. Winter-Spring 2001Codesign of Embedded Systems7 Introduction (cont’d) Exponential price/performance implies Paying for performance in a uni-processor is very expensive Using multiple small CPUs is cheaper Communication overhead is added, but still an economic choice Processors need not be CPUs. But special-function units. Special-purpose PEs can be even cheaper than dedicated CPU! Measured in system manufacturing cost, not necessarily in design cost

8. Winter-Spring 2001Codesign of Embedded Systems8 Introduction (cont’d) Reason 2: Scheduling overhead More than 31% overhead, under reasonable assumptions, when executing multiple processes Reason: uncertainty in the times at which the processes will need to execute Result: we have to reserve extra CPU horsepower, which comes at exponential cost

9. Winter-Spring 2001Codesign of Embedded Systems9 Introduction (cont’d) Still (1997) not quite possible to declare an authoritative taxonomy of co-synthesis models and methods Definition HW/SW co-synthesis: process of simultaneously design the SW architecture of an application and the HW architecture on which that SW is executed.

10. Winter-Spring 2001Codesign of Embedded Systems10 Introduction (cont’d) Problem Specification SW (app.) Arch. HW Engine PE Mem Communication Channels CoSynthesis

11. Winter-Spring 2001Codesign of Embedded Systems11 Introduction (cont’d) Problem specification includes Functionality Non-functional requirements Performance goals, physical constraints, etc

12. Winter-Spring 2001Codesign of Embedded Systems12 Introduction (cont’d) Hardware Architecture One or more Processing-Elements (PEs) Software (Application) Architecture includes Process structure Each process executes sequentially Allocation of the processes onto PEs in the HW engine Communication channels Hardware elements Software primitives

13. Winter-Spring 2001Codesign of Embedded Systems13 Introduction (cont’d) HW/SW Co-synthesis Allows trade-offs between SW architecutre and HW on which it executes Where is such trade-off important? Everyday processing applications vs. Embedded applications Different co-synthesis styles depending on The Specification The System Components System Elements to synthesize

14. Winter-Spring 2001Codesign of Embedded Systems14 Introduction (cont’d) Two broad implementation styles HW/SW partitioning Target HW architecture: a CPU and multiple ASICs Distributed System Co-synthesis Target HW architecture: arbitrary hardware topologies

15. Winter-Spring 2001Codesign of Embedded Systems15 Introduction to HW/SW Co-Synthesis Algorithms Preliminaries

16. Winter-Spring 2001Codesign of Embedded Systems16 Preliminaries Rate (execution rate) Maximum frequency at which a processing must be done Single-rate vs. Multi-rate Example of multi-rate system audio/video decoder

17. Winter-Spring 2001Codesign of Embedded Systems17 Preliminaries (cont’d) Latency Required maximum time between starting and finishing a processing task

18. Winter-Spring 2001Codesign of Embedded Systems18 Preliminaries (cont’d) Single-rate systems Standard model: Control-Data Flow Graph (CDFG) Implies a program-counter or system-state Software Control-Unit + Data path Not suitable to model multi-rate tasks unified system state

19. Winter-Spring 2001Codesign of Embedded Systems19 Preliminaries (cont’d) Multi-rate systems Common model: Task Graph Task Graph Each Node: Process Each Edge: Communication Each Set of connected nodes: sub-task P1 P2P3 P4P5 P6

20. Winter-Spring 2001Codesign of Embedded Systems20 What we learned today What’s co-synthesis Various keywords used in classification of co- synthesis algorithms

21. Winter-Spring 2001Codesign of Embedded Systems21 Complementary notes: Assignments Take Assignment 9 Due Date: Wednesday, Khordad 23th