1. EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 4 Technology Mapping

2. 2-Jul-15 PJF - 2Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)Overview More Logic Gates More Logic Gates NAND and NOR Gates NAND and NOR Gates NAND and NOR circuits NAND and NOR circuits Two-level Implementations Two-level Implementations Multilevel Implementations Multilevel Implementations Exclusive-OR (XOR) Gates Exclusive-OR (XOR) Gates Odd Function Odd Function Parity Generation and Checking Parity Generation and Checking

3. 2-Jul-15 PJF - 3Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) More Logic Gates We can construct any combinational circuit with AND, OR, and NOT gates We can construct any combinational circuit with AND, OR, and NOT gates Additional logic gates are used for practical reasons Additional logic gates are used for practical reasons

4. 2-Jul-15 PJF - 4Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) BUFFER, NAND and NOR

5. 2-Jul-15 PJF - 5Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) XOR and XNOR XY F = X  Y 000 011 101 110 Y F : “not-equal” gate XOR: “not-equal” gateXY F = X  Y 001 010 100 111 X Y F : “equal” gate XNOR: “equal” gate X

6. 2-Jul-15 PJF - 6Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) NAND Gate Known as a “universal” gate because ANY digital circuit can be implemented with NAND gates alone. Known as a “universal” gate because ANY digital circuit can be implemented with NAND gates alone. To prove the above, it suffices to show that AND, OR, and NOT can be implemented using NAND gates only. To prove the above, it suffices to show that AND, OR, and NOT can be implemented using NAND gates only.

7. 2-Jul-15 PJF - 7Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) NAND Gate Emulation X X X)’ F = (XX)’ = X’+X’ = X’+X’ = X’ = X’ X Y Y Y)’)’ F = ((XY)’)’ = (X’+Y’)’ = (X’+Y’)’ = X’’Y’’ = X’’Y’’ = XY = XY Y’)’ F = (X’Y’)’ = X’’+Y’’ = X’’+Y’’ = X+Y = X+Y X X X’ F = X’ X Y Y XY F XY = X+Y F = X+Y

8. 2-Jul-15 PJF - 8Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) NAND Circuits To easily derive a NAND implementation of a boolean function: To easily derive a NAND implementation of a boolean function: Find a simplified SOP Find a simplified SOP SOP is an AND-OR circuit SOP is an AND-OR circuit Change AND-OR circuit to a NAND circuit Change AND-OR circuit to a NAND circuit Use the alternative symbols below Use the alternative symbols below

9. 2-Jul-15 PJF - 9Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) AND-OR (SOP) Emulation Using NANDs a) Original SOP b) Implementation with NANDs Two-level implementations

10. 2-Jul-15 PJF - 10Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) AND-OR (SOP) Emulation Using NANDs (cont.) Verify: (a) G = WXY + YZ (b) G = ( (WXY)’ (YZ)’ )’ = (WXY)’’ + (YZ)’’ = WXY + YZ

11. 2-Jul-15 PJF - 11Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) SOP with NAND (again!) (a) Original SOP (b) Double inversion and grouping (c) Replacement with NANDs AND-NOT NOT-OR

12. 2-Jul-15 PJF - 12Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Two-Level NAND Gate Implementation - Example F (X,Y,Z) =  m(0,6) 1. Express F in SOP form: F = X’Y’Z’ + XYZ’ 2. Obtain the AND-OR implementation for F. 3. Add bubbles and inverters to transform AND-OR to NAND-NAND gates.

13. 2-Jul-15 PJF - 13Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example (cont.) Two-level implementation with NANDs F = X’Y’Z’ + XYZ’

14. 2-Jul-15 PJF - 14Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Multilevel NAND Circuits Starting from a multilevel circuit: 1. Convert all AND gates to NAND gates with AND-NOT graphic symbols. 2. Convert all OR gates to NAND gates with NOT-OR graphic symbols. 3. Check all the bubbles in the diagram. For every bubble that is not counteracted by another bubble along the same line, insert a NOT gate or complement the input literal from its original appearance.

15. 2-Jul-15 PJF - 15Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example Use NAND gates and NOT gates to implement Z=E’F(AB+C’+D’)+GH Use NAND gates and NOT gates to implement Z=E’F(AB+C’+D’)+GH AB AB AB+C’+D’ AB+C’+D’ E’F(AB+C’+D’) E’F(AB+C’+D’) E’F(AB+C’+D’)+GH E’F(AB+C’+D’)+GH

16. 2-Jul-15 PJF - 16Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Yet Another Example!

17. 2-Jul-15 PJF - 17Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) NOR Gate Also a “universal” gate because ANY digital circuit can be implemented with NOR gates alone. Also a “universal” gate because ANY digital circuit can be implemented with NOR gates alone. This can be similarly proven as with the NAND gate This can be similarly proven as with the NAND gate

18. 2-Jul-15 PJF - 18Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) NOR Circuits To easily derive a NOR implementation of a boolean function: To easily derive a NOR implementation of a boolean function: Find a simplified POS Find a simplified POS POS is an OR-AND circuit POS is an OR-AND circuit Change OR-AND circuit to a NOR circuit Change OR-AND circuit to a NOR circuit Use the alternative symbols below Use the alternative symbols below

19. 2-Jul-15 PJF - 19Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Two-Level NOR Gate Implementation - Example F(X,Y,Z) =  m(0,6) 1. Express F’ in SOP form: 1. F’ =  m(1,2,3,4,5,7) = X’Y’Z + X’YZ’ + X’YZ + XY’Z’ + XY’Z + XYZ 2. F’ = XY’ + X’Y + Z 2. Take the complement of F’ to get F in the POS form: F = (F’)' = (X'+Y)(X+Y')Z' 3. Obtain the OR-AND implementation for F. 4. Add bubbles and inverters to transform OR- AND implementation to NOR-NOR implementation.

20. 2-Jul-15 PJF - 20Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example (cont.) Two-level implementation with NORs F = (F’)' = (X'+Y)(X+Y')Z'

21. 2-Jul-15 PJF - 21Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Multilevel NOR Circuits Starting from a multilevel circuit: 1. Convert all OR gates to NOR gates with OR-NOT graphic symbols. 2. Convert all OR gates to NOR gates with NOT-AND graphic symbols. 3. Check all the bubbles in the diagram. For every bubble that is not counteracted by another bubble along the same line, insert a NOT gate or complement the input literal from its original appearance.

22. 2-Jul-15 PJF - 22Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Exclusive-OR (XOR) Function XOR (also  ) : the “not-equal” function XOR (also  ) : the “not-equal” function XOR(X,Y) = X  Y = X’Y + XY’ XOR(X,Y) = X  Y = X’Y + XY’ Identities: Identities: X  0 = X X  0 = X X  1 = X’ X  1 = X’ X  X = 0 X  X = 0 X  X’ = 1 X  X’ = 1 Properties: Properties: X  Y = Y  X X  Y = Y  X (X  Y)  W = X  ( Y  W) (X  Y)  W = X  ( Y  W)

23. 2-Jul-15 PJF - 23Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) XOR function implementation XOR(a,b) = ab’ + a’b XOR(a,b) = ab’ + a’b Straightforward: 5 gates Straightforward: 5 gates 2 inverters, two 2-input ANDs, one 2- input OR 2 inverters, two 2-input ANDs, one 2- input OR 2 inverters & 3 2-input NANDs 2 inverters & 3 2-input NANDs Nonstraightforward: Nonstraightforward: 4 NAND gates 4 NAND gates

24. 2-Jul-15 PJF - 24Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) XOR circuit with 4 NANDs

25. 2-Jul-15 PJF - 25Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Exclusive-NOR (XNOR) Function XNOR : the “equality” function XNOR : the “equality” function XNOR(a,b) = ab + a’b’ XNOR(a,b) = ab + a’b’ Observe that XNOR(a,b) = ( XOR(a,b) )’ Observe that XNOR(a,b) = ( XOR(a,b) )’ ( a  b )’ = ( a’b + ab’)’ = (a’b)’ (ab’)’ = (a + b’) (a’ +b) = ab + a’b’ ( a  b )’ = ( a’b + ab’)’ = (a’b)’ (ab’)’ = (a + b’) (a’ +b) = ab + a’b’ a  b’ = ( a  b )’ = a’  b a  b’ = ( a  b )’ = a’  b

26. 2-Jul-15 PJF - 26Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Odd Function x  y = x’y + xy’ x  y = x’y + xy’ x  y  z = xy’z’ + x’yz’ + x’y’z +xyz x  y  z = xy’z’ + x’yz’ + x’y’z +xyz x  y  z  w = x’yzw + xy’zw + xyz’w + xyzw’ + x’y’z’w + x’yz’w’ + x’y’zw’ +xy’z’w’ x  y  z  w = x’yzw + xy’zw + xyz’w + xyzw’ + x’y’z’w + x’yz’w’ + x’y’zw’ +xy’z’w’ … Observe a pattern here? … Observe a pattern here? An n-input XOR function is implied (=1) by all the minterms that have an odd # of 1s An n-input XOR function is implied (=1) by all the minterms that have an odd # of 1s Thus, XOR is also know as the odd function Thus, XOR is also know as the odd function

27. 2-Jul-15 PJF - 27Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Odd Function (cont.) Minterms are ALWAYS distance two from each other

28. 2-Jul-15 PJF - 28Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Odd Function (cont.)

29. 2-Jul-15 PJF - 29Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Even Function How would you implement an even function? How would you implement an even function? The complement of XOR  XNOR

30. 2-Jul-15 PJF - 30Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Parity Generation and Checking Odd and even functions can be used to implement parity checking circuits used for error detection and correction. Odd and even functions can be used to implement parity checking circuits used for error detection and correction. Use even parity as example. Use even parity as example. Parity generator: the circuit that generates the parity bit before transmitting. Parity generator: the circuit that generates the parity bit before transmitting. Parity checker: the circuit that checks the parity in the receiver. Parity checker: the circuit that checks the parity in the receiver.

31. 2-Jul-15 PJF - 31Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Even Parity Generation P(X,Y,Z) must produce a 1 for all the input combinations that contain an odd number of 1s P(X,Y,Z) must produce a 1 for all the input combinations that contain an odd number of 1s Thus, it is a 3-input odd function P = X  Y  Z Thus, it is a 3-input odd function P = X  Y  Z

32. 2-Jul-15 PJF - 32Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Even Parity Checking How would you implement a parity checker for the previous example? Use a 4-input XOR circuit (odd function) X  Y  Z  P C = X  Y  Z  P  1 indicates an error OR X  Y  Z  P)’ A 4-input XNOR circuit (even function) C = (X  Y  Z  P)’  1 indicates a pass

33. 2-Jul-15 PJF - 33Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Transmission Gates The transmission gate is one of the designs for an electronic switch for connecting and disconnecting two points in a circuit: The transmission gate is one of the designs for an electronic switch for connecting and disconnecting two points in a circuit: (a) X Y TG C C (c) C=0 and C=1 X Y (b) X Y C=1 and C=0 (d) X Y C TG

34. 2-Jul-15 PJF - 34Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Transmission Gates (continued) In many cases, X can be regarded as a data input and Y as an output. C and C, with complementary values applied, is a control input. In many cases, X can be regarded as a data input and Y as an output. C and C, with complementary values applied, is a control input. With these definitions, the transmission gate, provides a 3- state output: With these definitions, the transmission gate, provides a 3- state output: C = 1, Y = X (X = 0 or 1) C = 1, Y = X (X = 0 or 1) C = 0, Y = Hi-Z C = 0, Y = Hi-Z Care needs to be taken when using the TG in design, however, since X and Y as input and output are interchangeable, and signals can pass in both directions. Care needs to be taken when using the TG in design, however, since X and Y as input and output are interchangeable, and signals can pass in both directions.

35. 2-Jul-15 PJF - 35Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Exclusive OR F = A C Exclusive OR F = A C The basis for the function implementation is TG controlled paths to the output The basis for the function implementation is TG controlled paths to the output Circuit Example Using TG (b) A 0 0 1 1 C 0 1 0 1 TG1 No path Path No path Path TG0 Path No path Path No path F 0 1 1 0 (a) C A F TG0 TG1 +

36. 2-Jul-15 PJF - 36Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) More Complex Gates The remaining complex gates are SOP or POS structures with and without an output inverter. The remaining complex gates are SOP or POS structures with and without an output inverter. The names are derived using: The names are derived using: A - AND A - AND O - OR O - OR I - Inverter I - Inverter Numbers of inputs on first-level “gates” or directly to second-level “gates” Numbers of inputs on first-level “gates” or directly to second-level “gates”

37. 2-Jul-15 PJF - 37Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) More Complex Gates (continued) Example: AOI - AND-OR-Invert consists of a single gate with AND functions driving an OR function which is inverted (page 95 in the textbook). Example: AOI - AND-OR-Invert consists of a single gate with AND functions driving an OR function which is inverted (page 95 in the textbook). These gate types are used because: These gate types are used because: The number of transistors needed is fewer than required by connecting together primitive gates The number of transistors needed is fewer than required by connecting together primitive gates Potentially, the circuit delay is smaller, increasing the circuit operating speed Potentially, the circuit delay is smaller, increasing the circuit operating speed

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