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Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Verilog Part 2 – Chapter 5 – Behavioral and Hierarchical Descriptions Logic and Computer Design Fundamentals
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Verilog - Part 2 2 Overview Part 2 Behavioral Descriptions Using: Assignment statements Higher level operators Verilog Hierarchy Using: Modules Module instantiation Example: Adder-Subtractor Assignment statements using addition operator and vector XOR operator Hierarchy with adder module and 1’s complementer module
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Verilog - Part 2 3 Behavioral & Hierarchical Verilog Example Circuit function can be described by assign statements at higher than the logic level: module addsub (A, B, R, sub); input [3:0] A, B; output [3:0] R; input sub; //sub ? subtract : add wire[3:0] data_out //Instantiate add and M1comp modules add A1 (A, data_out, sub, R); M1comp C1 (B, data_out, sub); endmodule
![Verilog - Part 2 3 Behavioral & Hierarchical Verilog Example Circuit function can be described by assign statements at higher than the logic level: module addsub (A, B, R, sub); input [3:0] A, B; output [3:0] R; input sub; //sub .](http://images.slideplayer.com/16/4910901/slides/slide_3.jpg "subtract : add wire[3:0] data_out //Instantiate add and M1comp modules add A1 (A, data_out, sub, R); M1comp C1 (B, data_out, sub); endmodule.")
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Verilog - Part 2 4 Behavioral & Hierarchical Verilog Example (continued) module add (X, Y, C_in, S); input [3:0] X, Y; input C_in; output [3:0] S; assign S = X + Y + {3'b0, C_in}; endmodule module M1comp (data_in, data_out, comp); input[3:0] data_in; input comp; output [3:0] data_out; assign data_out = {4{comp}} ^ data_in; endmodule // {n{x}} means concatenate // n copies of x
![Verilog - Part 2 4 Behavioral & Hierarchical Verilog Example (continued) module add (X, Y, C_in, S); input [3:0] X, Y; input C_in; output [3:0] S; assign S = X + Y + {3 b0, C_in}; endmodule module M1comp (data_in, data_out, comp); input[3:0] data_in; input comp; output [3:0] data_out; assign data_out = {4{comp}} ^ data_in; endmodule // {n{x}} means concatenate // n copies of x](http://images.slideplayer.com/16/4910901/slides/slide_4.jpg "Verilog - Part 2 4 Behavioral & Hierarchical Verilog Example (continued) module add (X, Y, C_in, S); input [3:0] X, Y; input C_in; output [3:0] S; assign S = X + Y + {3 b0, C_in}; endmodule module M1comp (data_in, data_out, comp); input[3:0] data_in; input comp; output [3:0] data_out; assign data_out = {4{comp}} ^ data_in; endmodule // {n{x}} means concatenate // n copies of x")
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Verilog - Part 2 5 Terms of Use © 2004 by Pearson Education,Inc. All rights reserved. The following terms of use apply in addition to the standard Pearson Education Legal Notice.Legal Notice Permission is given to incorporate these materials into classroom presentations and handouts only to instructors adopting Logic and Computer Design Fundamentals as the course text. Permission is granted to the instructors adopting the book to post these materials on a protected website or protected ftp site in original or modified form. All other website or ftp postings, including those offering the materials for a fee, are prohibited. You may not remove or in any way alter this Terms of Use notice or any trademark, copyright, or other proprietary notice, including the copyright watermark on each slide. Return to Title Page Return to Title Page
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