PPI 8255 It is an I/O port chip used for interfacing I/O devices with microprocessor. The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. The Intel’s 8255 is designed for use with Intel’s 8-bit, 16- bit microprocessors.
PPI 8255 It has 24 input/output lines which may be individually programmed in groups. The groups of I/O pins are named as Group A, Group B and group C upper and Group C lower. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4- bit port.
PPI 8255 The port A lines are identified by symbols PA 0 -PA 7 while the port C lines are identified as PC 4 -PC 7. Similarly, Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C with lower bits PC0- PC3. All of these ports can function independently either as input or as output ports. This can be achieved by programming the bits of an internal register of 8255 called as control word register ( CWR ).
Two control groups, labeled group A control and group B control define how the three I/O ports operate. One of the 4 bit group is associated with group A control and the other 4 bit group with group B control device signals. The upper 4 bits of port C are associated with group A control while the lower 4 bits are associated with group B control. The final logic blocks are read/write control logic and data bus buffer.
Block Diagram of 8255 These blocks provide the electrical interface between the micro processor and 8255. The data bus buffer buffers the data I/O lines to/from the microprocessor data bus. The read/write control logic routes the data to and from the correct internal registers with the right timing.
The 8255 is a 40 pin integrated circuit (IC), designed to perform a variety of interface functions in a computer environment. D0 - D7 These are the data input/output lines for the device. All information read from and written to the 8255 occurs via these 8 data lines. CS (Chip Select Input). If this line is a logical 0, the microprocessor can read and write to the 8255. RD (Read Input) Whenever this input line is a logical 0 and the CS input is a logical 0, the 8255 data outputs are enabled onto the system data bus.
Pin Diagram of 8255 WR (Write Input) Whenever this input line is a logical 0 and the CS input is a logical 0, data is written to the 8255 from the system data bus A0 - A1 (Address Inputs) The logical combination of these two input lines determines which internal register of the 8255 data is written to or read from. RESET The 8255 is placed into its reset state if this input line is a logical 1. All peripheral ports are set to the input mode.
Pin Diagram of 8255 PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports. They can be connected to peripheral devices. The 8255 has three 8 bit I/O ports and each one can be connected to the physical lines of an external device. These lines are labeled PA0-PA7, PB0-PB7, and PC0-PC7. The groups of the signals are divided into three different I/O ports labeled port A (PA), port B (PB), and port C (PC).
Modes of 8255 There are two basic modes of operation of 8255, They are: 1. I/O mode. 2. BSR mode. In I/O mode, the 8255 ports work as programmable I/O ports, while In BSR mode only port C (PC0-PC7) can be used to set or reset its individual port bits.
Modes of 8255 There are 3 I/O modes of operation for the ports of 8255. Mode 0, Mode 1, and Mode 2 1) Mode 0 - Basic I/O mode 2) Mode 1 - Strobed I/O mode 3) Mode 2 - Strobed bi-directional I/O
Modes of 8255 Mode 0 Operation It is Basic or Simple I/O. It does not use any handshake signals. It is used for interfacing an i/p device or an o/p device. It is used when timing characteristics of I/O devices is well known
Modes of 8255 Mode 1 Operation It uses handshake I/O. 3 lines are used for handshaking. It is used for interfacing an i/p device or an o/p device. Mode 1 operation is used when timing characteristics of I/O devices is not well known, or used when I/O devices supply or receive data at irregular intervals.
Modes of 8255 Handshake signals of the port inform the processor that the data is available, data transfer complete etc. Mode 2 Operation It is bi-directional handshake I/O. Mode 2 operation uses 5 lines for handshaking. It is used with an I/O device that receives data some times and sends data sometimes. Mode 2 operation is useful when timing characteristics of I/O devices is not well known, or when I/O devices supply or receive data at irregular intervals.
Modes of 8255 Port A, Port B and Port C can work in Mode 0 Port A and Port B can work in Mode 1 Only Port A can work in Mode 2
Programmable Interrupt Controller The 8085 has only 5 interrupt line. If I/O devices need more interrupt line to transfer data, we go for Programmable Interrupt controllers. The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for the Intel 8085 and Intel 8086 microprocessors.
Programmable Interrupt Controller In computing, a programmable interrupt controller (PIC) is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs.
Programmable Interrupt Controller 8259 PICs typically have a common set of registers: Interrupt Request Register (IRR), In-Service Register (ISR), Interrupt Mask Register (IMR). The IRR sores the interrupts request that is coming from 8 interrupt lines The ISR register stores all the interrupts that are currently being serviced The IMR stores the masking bits ie which interrupts are to be ignored and not acknowledged.
There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). Data bus buffer and read-write logic: are used to configure the internal registers of the chip. Interrupt mast register (IMR): is used to enable or mask out the individual interrupt inputs through bits M0 to M7. 0= enable, 1= masked out. Interrupt request register (IRR): is used to indicate all interrupt levels requesting service.
Block Diagram of PIC 8259 In service register (ISR): is used to store all interrupt levels which are currently being serviced. Priority resolver: This block determines the priorities of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during the INTA sequence. Cascade-buffer comparator: Sends the address of the selected chip to the slaves in the master mode and decodes the status indicated by the master to find own address to respond.
Block Diagram of PIC 8259 One or more of the INTERRUPT REQUEST lines (IR0 - IR7) are raised high, setting the corresponding IRR bit(s). The 82C59A evaluates those requests in the priority resolver and sends an interrupt (INT) to the CPU, if appropriate. The CPU acknowledges the lNT and responds with an INTA pulse. The 82C59 does not drive the data bus during the first INTA pulse.
Block Diagram of PIC 8259 During this INTA pulse, the appropriate ISR bit is set and the corresponding bit in the IRR is reset. This completes the interrupt cycle. In the AEOI mode, the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.
Eight interrupt input request lines named IRQ0 through IRQ7, An interrupt request output line named INTR, Interrupt acknowledgment line named INTA, D0 through D7 for communicating the interrupt level or vector offset. Other connections include CAS0 through CAS2 for cascading between 8259s.
The 8259 programmable interrupt controller (PIC) adds eight vectored priority encoded interrupts to the microprocessor. This controller can be expanded without additional hardware to accept up to 64 interrupt requests. This requires a master 8259 and eight 8259 slaves. 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.
Command Words of 8259 The command words of 8259A are classified in two groups 1. Initialization command words (ICW) and 2. Operation command words (OCW) Initialization Command Words (ICW): Before it starts functioning, the 8259 must be initialized by writing two to four command words into the respective command word registers. These are called as initialized command words
PIT 8254/8253 The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting functions. They were primarily designed for the Intel 8080/8085- processors. After the desired delay, the 8254 will interrupt the CPU. It is 24 pin IC requires +5 V It consists of 3 16 bit counters operates in 6 modes.
PIT 8254 It generates accurate time delays under software control. Instead of setting up timing loops in software, the programmer configures the interval timer to match system requirements and programs the counter for the desired delay or for the desired output. Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are
Data/Bus Buffer This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. It has 8 input pins, usually labeled as D7..D0, where D7 is the MSB
Block Diagram of 8254/8253 Read/Write Logic RD: read signal /WR: write signal /CS: chip select signal A0, A1: address lines Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.
Block Diagram of 8254/8253 The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.
Counters There are 3 counters (or timers), which are labeled as "Counter 0", "Counter 1" and "Counter 2. Each counter has 2 input pins – "CLK" (clock input) and "GATE" and 1-pin, "OUT", for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.
Block Diagram of 8254/8253 Counters are programmed by writing a Control Word and then an initial count. GATE=1 enables counting, GATE=0 disables counting. All 3 counters are 16-bits. PIT has only an 8-bit data bus and can read or write only one byte at a time. Thus to read or write a 16-bit value, you must do so one byte at a time.
Block Diagram of 8254/8253 For example, to load counter0 with 38370 decimal, the LSB is 226 decimal, and its MSB is 149 decimal (Figure).
Programming of 8254 1. Counters are programmed by writing a Control Word and then an initial count. 2. Control Words are written into the Control Word Register, which is selected when A0,A1=11. The Control Word itself specifies which Counter is being programmed. 3. Initial counts are written into the Counters, not the Control Word Register. The A0,A1 inputs are used to select the Counter to be written into. 4. The format of the initial count is determined by the Control Word used.
There are 5 steps to calculate the proper control word number: Step 1: Chose one counter (SC1 and SC0) Step 2: Chose method to load (RW1 and RW0) Step 3: Chose programming mode (M2, M1 and M0) Step 4: Chose binary or BCD number (BCD). Step 5: Convert the final binary word into decimal
Control Word of PIT 8254 A0 and A1 select one of the three counters or the control word register to be read from/written into as specified in the following table. Example Suppose you want to make counter 0 a binary counter that generates square waves, and uses LSB and MSB read/write loading. What is the proper control word?
Control Word of PIT 8254 Figure shows the answer. From Step 1, SC1 and SC0 both are 0 if you want to use counter 0. Step 2 say that LSB and MSB are both loaded. For square wave generation, you use Mode 3 and Step 3 says that M2,M1,M0 = 011. Step 4 makes BCD = 0 to have a binary counter. Thus the resulting binary number is 00110110 or, 54 decimal. Thus you would load the control register with controlWord with 54:
Operating Modes PIT 8254 There are six modes of operation for the counters. In all modes the counters operate as down counters. They are defined as follows: Mode 0: Interrupt on Terminal Count/ Event counter Mode 1: Hardware Re triggerable One-Shot Mode 2: Rate Generator Mode 3: Square Wave Mode Mode 4: Software Triggered Strobe Mode 5: Hardware Triggered Strobe (Re triggerable)
Operating Modes PIT 8254 MODE 0: Interrupt on terminal count 1. Event counting. 2. After the Control Word is written, OUT is initially low and remains low. 3. When the counter reaches zero. OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter.
Operating Modes PIT 8254 MODE 1: Hardware retriggerable one-shot 1. OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and remain low until the Counter reaches zero. 2. OUT will then go high and remain high until the CLK pulse after the next trigger.
Operating Modes PIT 8254 MODE 2: Rate generator 1. Functions like a divide-by-N counter and used to generate a Real Time Clock interrupt. 2. OUT will initially be high. 3. When the initial count has decremented to one, OUT goes low for one CLK pulse. 4. Out then goes high again, the Counter reloads the initial count and the process is repeated. 5. MODE 2 is periodic. The same sequence is repeated indefinitely.
Operating Modes PIT 8254 MODE 3: Square wave mode 1. Typically used for baud rate generation. 2. Out will initially be high. 3. When half the initial count is expired, OUT goes low for the remainder of the count. 4. MODE 3 is periodic. The same sequence is repeated indefinitely.
Operating Modes PIT 8254 MODE 4: Software triggered strobe 1. OUT will initially be high. 2. When the initial count expires, OUT will go low for one CLK pulse and then go high again. 3. The counting sequence is "triggered" by writing the initial count. 4. The Counter is loaded on the next CLK pulse following writing a Control Word and initial count.
Operating Modes PIT 8254 MODE 5: Hardware triggered strobe (retriggerable) 1. OUT will initially be high. 2. Counting is triggered by a rising edge of GATE. 3. When the initial count expires, OUT will go low for one CLK pulse and then go high again. 4. The difference between MODE 4 and MODE 5 is that in MODE 5 the count will not be loaded until the CLK pulse after a trigger.
The direct memory access (DMA) I/O technique provides direct access to the memory while the microprocessor is temporarily disabled. DMA controller: dedicated hardware used for controlling the DMA operation A DMA controller temporarily borrows the address bus, data bus, and control bus from the microprocessor and transfers the data bytes directly between an I/O port and a series of memory locations.
DMA controller The DMA transfer is also used to do high-speed memory-to memory transfers. Two control signals are used to request and acknowledge a DMA transfer in the microprocessor-based system. The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses after the current bus cycle. The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released control of its buses by placing the buses at their high-impedance states.
Comparison between DMA controllers Commonly used programmable DMA controllers are 8237 and 8257
Programmable DMA Controller 8237 The 8237 is a four-channel device that can be expanded to include any number of DMA channel inputs. The 8237 is capable of DMA transfers at rates of up to 1.6 M Byte per second. Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k bytes with a single programming.
The 8237A block diagram includes the major logic blocks and all of the internal registers. The 8237A contains three basic blocks of control logic. The Timing Control block generates internal timing and external control signals for the 8237A. The Program Command Control block decodes the various commands given to the 8237A by the micro-processor prior to servicing a DMA Request.
Block Diagram of 8237 It also decodes the Mode Control word used to select the type of DMA during the servicing. The Priority Encoder block resolves priority contention between DMA channels requesting service simultaneously The 8237A is designed to operate in two major cycles. These are called Idle and Active cycles.
Block Diagram of 8237 The 8237A contains 344 bits of internal memory in the form of registers.
Block Diagram of 8237 Command Register This 8-bit register controls the operation of the 8237A. It is programmed by the microprocessor in the Program Condition and is cleared by Reset or a Master Clear instruction. The following table lists the function of the command bits. Mode Register Each channel has a 6-bit Mode register associated with it. When the register is being written to by the microprocessor in the Program Condition, bits 0 and 1 determine which channel Mode register is to be written
Block Diagram of 8237 Request Register The 8237A can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are non-maskable and subject to prioritization by the Priority Encoder network.
Modes of 8237 The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used. Single - One DMA cycle, one CPU cycle interleaved until address counter reaches zero. Block - Transfer progresses until the word count reaches zero or the EOP signal goes active.
Modes of 8237 Demand - Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested. Cascade - Used to cascade additional DMA controllers. DREQ and DACK is matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals is executed by cascaded chip.
8279 The Intel 8279 is a Keyboard/Display Controller is specially developed for interfacing keyboard and display devices for the Intel 8085, 8086 Microprocessors. The device is well suited for driving seven or eighteen segment display units and for interfacing matrix key boards.
DB 0 -DB 7 : These are bidirectional data bus lines. The data and command words to and from the CPU are transferred on these lines. RD, WR ( Input / Output ) READ/WRITE :These input pins enable the data buffers to receive or send data over the data bus. A0(Address lines) : A high on this line indicates the transfer of a command or status information. A low on this line indicates the transfer of data. This is used to select one of the internal registers of 8279.
8279 CS : Chip Select – A low on this line enables 8279 for normal read or write operations. Other wise, this pin should remain high. RESET : This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279, its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set to 31. CLK : This is a clock input used to generate internal timing required by 8279.
8279 IRQ : This interrupt output lines goes high when there is a data in the FIFO sensor RAM. The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM further contains any key- code entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU. Vss, Vcc : These are the ground and power supply lines for the circuit. SL0-SL3-Scan Lines : These lines are used to scan the key board matrix and display digits. These lines can be programmed as encoded or decoded, using the mode control register.
8279 RL0 - RL7 - Return Lines : These are the input lines which are connected to one terminal of keys, while the other terminal of the keys are connected to the decoded scan lines. These are normally high, but pulled low when a key is pressed. SHIFT : The status of the shift input lines is stored along with each key code in FIFO, in scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with a key closure. CNTL/STB- CONTROL/STROBED I/P Mode : In keyboard mode, this lines is used as a control input and stored in FIFO on a key closure. The line is a strobed lines that enters the data into FIFO RAM, in strobed input mode. It has an interrupt pull up. The lines is pulled down with a key closer.
8279 OUT A0 – OUT A3 and OUT B0 – OUT B3 : These are the output ports for two 16*4 or 16*8 internal display refresh registers. The data from these lines is synchronized with the scan lines to scan the display and keyboard. The two 4-bit ports may also as one 8-bit port. BD – Blank Display : This output pin is used to blank the display during digit switching or by a blanking closure.
It consists 4 main section. 1. CPU interface and control section. 2. Scan section 3. Keyboard Section 4. Display section. CPU INTERFACE AND CONTROL SECTION: It consists of 1. Data buffers 2. I/O control 3. Control and timing registers. 4. Timing and control logic.
Block Diagram of 8279 Data Buffers: 8-bit bidirectional buffer. Used to connect the internal data bus and external data bus. I/O control: I/O control section uses the A0,CS,RD and WR signals to controls the data flow. The data flow is enabled by CS=0otherwise it is the high impedance state. A0=0 means the data is transferred. A0=1 means status or command word is transferred.
Block Diagram of 8279 TIMING AND CONTROL REGISTERS: Store the keyboard and display modes and others operating condition programmed by the CPU. The modes are programmed by sending proper command A 0 =1. TIMING AND CONTROL: It consist timing counter chain. First counter is divided by N prescalar that can be programmed to give an internal frequency of 100 KHz.
8279 Modes The modes of operation of 8279 are as follows : 1. Input (Keyboard) modes. 2. Output (Display) modes. Input ( Keyboard ) Modes : 8279 provides three input modes. These modes are as follows Scanned Keyboard Mode : This mode allows a key matrix to be interfaced using either encoded or decoded scans. In encoded scan, an 8*8 keyboard or in decoded scan, a 4*8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL status is stored into the FIFO RAM
8279 Modes Scanned Sensor Matrix : In this mode, a sensor array can be interfaced with 8279 using either encoded or decoded scans. With encoded scan 8*8 sensor matrix or with decoded scan 4*8 sensor matrix can be interfaced. The sensor codes are stored in the CPU addressable sensor RAM. 3. Strobed input : In this mode, if the control lines goes low, the data on return lines, is stored in the FIFO byte by byte
8279 Modes Output (Display) Modes : 8279 provides two output modes for selecting the display options. These are discussed briefly. 1. Display Scan : In this mode 8279 provides 8 or 16 character multiplexed displays those can be organized as dual 4- bit or single 8-bit display units. 2. Display Entry : ( right entry or left entry mode ) 8279 allows options for data entry on the displays. The display data is entered for display either from the right side or from the left side
8279 Modes Scanned Keyboard mode with 2 Key Lockout : In this mode of operation, when a key is pressed, a debounce logic comes into operation. During the next two scans, other keys are checked for closure and if no other key is pressed the first pressed key is identified. The key code of the identified key is entered into the FIFO with SHIFT and CNTL status, provided the FIFO is not full, i.e. it has at least one byte free. If the FIFO does not have any free byte, naturally the key data will not be entered and the error flag is set.