1. Revision Mid 2 Prof. Sin-Min Lee Department of Computer Science

13. Example: Determine the product term for the K- Map below and write the resulting minimum SOP expression 1

15. Example: Use a K-Map to minimize the following standard SOP expression

17. Mapping Directly from a Truth Table

18. Don’t Care (X) Conditions A situation arises in which input variable combinations are not allowed Don’t care terms either a 1 or a 0 may be assigned to the output

19. Don’t Care (X) Conditions Example of the use of “don’t care” conditions to simplify an expression

20. Exercise: Use K-Map to find the minimum SOP from 1 2

21. JK Flip-flop The most versatile of the flip-flops Has two data inputs (J and K) Do not have an undefined state like SR flip- flops – When J & K both equal 1 the output toggles on the active clock edge Most JK flip-flops based on the edge- triggered principle J K Q Q JKCQ n+1 00  Q n Hold 01  0Reset 10  1Set 11  Q n Toggle XXXQ n Hold +ve edge triggered JK flip-flop The C column indicates +ve edge triggering (usually omitted)

22. Timing diagram for JK Flip-flop cloc k J K Q toggle J=K=1 hold J=K=0 reset J= 0 K=1 set J= 1 K=0 Negative Edge Triggered

23. JK from D Flip-flop D C Q Q’ J K CLK

24. Implementing with a D AND a T flip-flop Using this FSM with three states, an operating only on inputs and transitions from one state to another, we will be using both D and T flip-flops.

25. Implementing with a D AND a T flip-flop Since we have no state “11”, our Q(t+1) is “don't care” = “XX” for both of these transitions. Consider the first column of the Q(t+1) values to be “D” and the second to be “T” and then we derive two corresponding charts. DT

26. Implementing with a D AND a T flip-flop Then we need to derive the corresponding equations.

27. Implementing with a D AND a T flip-flop We assume that Q(t) is actually a pair of Q D Q T. Now, with these equations, we can graph the results.

28. Implementing with a D AND a T flip-flop

29. XQ1Q0Q1+Q0+Y 00001X 001010 01000X 011XXX 10010X 101101 110XXX 111XXX A A C C B B 0/0 0/- 1/1 0/- 1/- 1/1 00 01 10 X/Y X= input Y=output X = don’t care

30. X\Q0Q100011110 000X0 111XX X\Q0Q100011110 011X0 100XX X\Q0Q100011110 000X1 111XX T T = X + Q1 JK X\Q0Q100011110 011X0 100XX X\Q0Q100011110 011X0 100XX J = X’Q’K = X

31. Using T Flip Flop and JK Flip Flop log 2 4 = 2, so 2 flip flops are needed to implement this FSA

32. Step 1 - Translate diagram into State Table

33. Step 2 - Create maps for T and JK

34. Step 3 - Determine T, J, and K equations

35. Step 4 - Draw resulting diagram

36. 36 Figure 9--15 Timing diagram for the counter

37. 37 Figure 9--68 State diagram showing the 2-bit Gray code sequence.

38. 38 Figure 9--69 Sequential logic.

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42. Memory Technology Static RAM (SRAM) – 0.5ns – 2.5ns, $2000 – $5000 per GB Dynamic RAM (DRAM) – 50ns – 70ns, $20 – $75 per GB Magnetic disk – 5ms – 20ms, $0.20 – $2 per GB Ideal memory – Access time of SRAM – Capacity and cost/GB of disk

43. Principle of Locality Programs access a small proportion of their address space at any time Temporal locality – Items accessed recently are likely to be accessed again soon – e.g., instructions in a loop, induction variables Spatial locality – Items near those accessed recently are likely to be accessed soon – E.g., sequential instruction access, array data

44. Taking Advantage of Locality Memory hierarchy Store everything on disk Copy recently accessed (and nearby) items from disk to smaller DRAM memory – Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory – Cache memory attached to CPU

45. Memory Hierarchy Levels Block (aka line): unit of copying – May be multiple words If accessed data is present in upper level – Hit: access satisfied by upper level Hit ratio: hits/accesses If accessed data is absent – Miss: block copied from lower level Time taken: miss penalty Miss ratio: misses/accesses = 1 – hit ratio – Then accessed data supplied from upper level

46. Cache Memory Cache memory – The level of the memory hierarchy closest to the CPU Given accesses X 1, …, X n–1, X n How do we know if the data is present? Where do we look?

47. The Cache Hit Ratio How often is a word found in the cache? Suppose a word is accessed k times in a short interval – 1 reference to main memory – (k-1) references to the cache The cache hit ratio h is then

48. Reasons why we use cache Cache memory is made of STATIC RAM – a transistor based RAM that has very low access times (fast) STATIC RAM is however, very bulky and very expensive Main Memory is made of DYNAMIC RAM – a capacitor based RAM that has very high access times because it has to be constantly refreshed (slow) DYNAMIC RAM is much smaller and cheaper

49. Performance (Speed) Access time – Time between presenting the address and getting the valid data (memory or other storage) Memory cycle time – Some time may be required for the memory to “recover” before next access – cycle time = access + recovery Transfer rate – rate at which data can be moved – for random access memory = 1 / cycle time (cycle time) -1

50. 50 Figure 9--70

51. 51 Figure 9--71