1. Chapter 8 Synchronous Sequential Circuits 同步时序电路 1.use flip-flops to represent the states of the circuit ; 2.use clock pulses to trigger changes in the states. 3.realized using combinational logic and one or more flip-flops.

2. state The value of the outputs of the flip-flops are referred to the state. Active clock edge Outputs=Function(present state, present inputs)

3. Moore & Mealy Moore type:circuits whose outputs depend only on the state of the circuits. ______Edward Moore Mealy type: circuits whose outputs depend both the state and the present inputs of the circuits. ______George Mealy

4. FSM Finite State Machines (FSMs) 有限状态机 ASM Algorithmic State Machine 算术状态机（流程图） 状态、判决、条件

5. Specification 技术规格 1.The circuit has one input,w,and one output,z; 2.All changes in the circuit occur on the positive edge of a clock signal; 3.The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1.Otherwise, the value of z is equal to 0.

6. State Diagram 状态图 State number Starting state Pictorial representation

7. State Table 状态表 Tabular form: Present state Next state Output

8. State Assignment 状态赋值 State variables___flip-flop n state, n-1 state variables; Next state variables: Y1,Y2 （大写） ; Present state variables: y1,y2 ( 小写） ; State-assigned table 状态赋值表

9. One-hot Encoding “ 独热 ” 编码 Only one state variable is equal to 1__one hot, others are equal to 0

10. VHDL Code for FSMs Moore state Mealy state

11. ARCHITECTURE (Moore) TYPE State_type IS(A,B,C); SIGNAL y: State_type; CASE y IS WHEN A=> IF w=‘0’ THEN y<=A; ELSE y<=B; END IF;

12. WHEN B=> IF w=‘0’ THEN y<=A; ELSE y<=C; END IF;

13. WHEN C=> IF w=‘0’ THEN y<=A; ELSE y<=C; END IF;

14. END CASE; END IF; END PROCESS; z<=‘1’ WHEN y=C ELSE ‘0’; END Behavior;

15. SIGNAL y_present,y_next: State_type; CASE y_present IS y_next<=A; PROCESS(Clock,Resentn) y_present<=y_next;

16. ARCHITECTURE (Mealy) TYPE State_type IS(A,B); PROCESS(y,w) CASE y IS WHEN A => z<=‘0’; WHEN B=> z<=‘w’; END CASE; END PROCESS;

17. Serial Adder Example Shift register FSM serial (full_adder)