1. University of California, Irvine D. Hawkins, A. Lankford, M. Medve, S. Pier, M. Schernau, S. Shim, D. Stoker Brookhaven National Laboratory A. Gordeev, V. Gratchev, S. Junnarkar, A. Kandasamy, P. O’Connor, V. Polychronakos, V. Tcherniatine Cathode Strip Chambers

6. DSP Module

7. Testing in the Lab PC-based National Instruments VME interface Microsoft Visual C++ PC-DAQ Joint test of On-Chamber electronics DSP debugging with Texas Instruments Code Composer Studio

8. ROD Facts Number of RODs:16 in initial stage, 32 final stage Number of ROD crates: 2 One partition per endcap Fragment size: 200 Bytes (with safety factor of 5) Input bandwidth: 1.1 Gbytes/s/ROD Output bandwidth: 20 Mbytes/s/ROD Reset times: 3 s Powerup from Flash memory

9. Configuration data size FPGA: 1.5 Mbytes per ROD DSP: 1 Mbyte per ROD Calibration constants: 9.6 kBytes per ROD To be loaded over VME backplane

10. Future Plans Fully functional ROD ready for production at the end of 2003 Flexible output format due to DSP code written in C Continue ROD DSP software development Want two ROD crates and RCCs by March 2003 for software development and system integration tests

11. Future Plans Beam test in 2003 possible We expect a combined test beam run with other detectors in 2004 Use in precommissioning of small wheels on surface during late 2005 possible Installation in USA15 scheduled for May 2006