1. A new servo controller for a Materials Testing Machine - MTM Final Presentation B Students : Uri Goldfeld & David Schwartz Supervisor : Daniel Alkalay & Amir Reoven

2. General System Description The MTM system we work on is a mechanical system that allows us to test the physical properties of materials and structures. Testing is done by applying static or dynamic loads, using an hydraulic actuator in closed-loop servo control. Feedback for closed loop control uses displacement OR Strain sensors. The MTM system enables us to determine tensile/compressive strength, fatigue resistance, crack growth resistance ect.

3. The Original System

4. Main Project Goals The global purpose is to develop a modern computer based mechanical testing system, using current hardware and software tools. Part A: Part B: Servo+hydraulics Old control system FPGALabView Softwarecontroller

5. Goals achieved Part A Learning LabVIEW Learning LabVIEW Learning the required control tools Learning the required control tools Performing system identification Performing system identification Implementation of a simulation environment Implementation of a simulation environment Simulate the whole system using our controller Simulate the whole system using our controller Keeping the environment General Keeping the environment General

6. Hardware: - E series 6036 DAQ card - M series 6122 DAQ card - M series 6122 DAQ card - hp33120 waveform generator - hp33120 waveform generator via RS232 via RS232 Software: - NI LabVIEW 7.1 - DaqMx toolbox - DaqMx toolbox - PID toolbox - PID toolbox

7. Project Goals of Part B: Learn LabVIEW FPGA module Learn LabVIEW FPGA module Learn LabVIEW RT module Learn LabVIEW RT module Build the control system in FPGA Build the control system in FPGA Generate all required experiment waveforms Generate all required experiment waveforms Build a general system which can be easily adjusted when hardware is changed Build a general system which can be easily adjusted when hardware is changed Allow control on most functions and parameters Allow control on most functions and parameters Build an “easy to use” GUI Build an “easy to use” GUI

8. Hardware: - PXI 8187 chassis - PXI 8187 chassis - NI FPGA PXI-7811R - NI FPGA PXI-7811R - Valve driver (amplifier) - Valve driver (amplifier) - LVDT signal conditioner - LVDT signal conditioner - Load Cell signal conditioner - Load Cell signal conditioner - Power supply - Power supplySoftware: - LabVIEW 7.1 - LabVIEW 7.1 - LabVIEW FPGA module - LabVIEW FPGA module

9. LabVIEW FPGA module The LabVIEW FPGA program consists of two parts: 1. host VI 2. FPGA VI The Host VI executes on windows and the FPGA VI must be compiled and downloaded to FPGA.

10. New system overview LabVIEW windows LabVIEW windows Signal generation Gui, configurations FPGAFPGA 7831R FPGA PID, Limit check Interlock check PXI 8187 Lvdt conditioner Load Cell conditioner valve driver Powersupply Lvdt Load Cell Valve

11. LabVIEWwindows Inputs Outputs to FPGA User configurations User configurations [physical] User configurations PV from FPGA Limits status Set Point (encoder) PID Parameters Limits [V] Stimulus signal [V] Stimulus signal [V]configurations

12. User configurations Choose control sensor and limit sensor Choose control sensor and limit sensor Configure Limits for load (Kg) and displacement Configure Limits for load (Kg) and displacement (cm) (cm)

13. User configurations (cont.) Waveform type, amplitude, frequency Waveform type, amplitude, frequency PID parameters (optional) PID parameters (optional) Sensor Calibration parameters (optional) Sensor Calibration parameters (optional) return

14. Signal Generation User specification are in physical units i.e User specification are in physical units i.e Kg, cm, mm/min Kg/min Kg, cm, mm/min Kg/min Signals supported – sine, ramp, square, Signals supported – sine, ramp, square, idle, set point, triangle, haversine, havertriangle, haversquare. havertriangle, haversquare.

15. Userconfigurations Unitconverts Amplitude & Freq. calc Signal type SignalGeneration limits mux Idle Master int. Signal type V2B FPGA Initialization data Amplitude & Freq

16. VI hierarchy return

17. FPGA 7831R 7831R Details Inputs Outputs Inputs Outputs Internal: Response signals to windows Limits check result to windows Configurations from windows LVDT conditioner Load Cell conditioner Optional feature: Optional feature: internal “signal conditioner” to LVDT (get response “sine”) Optional feature: External: Stimulus signal to “Valve driver” send stimulus “sine” and calculat the valve’s location “Hard” interlocks

18. FPGA 8187 details Hardware: NI PXI-7811R: Hardware: NI PXI-7811R: - 1M gate FPGA, 160 DIO for PXI - 1M gate FPGA, 160 DIO for PXI - 16 bit A/D,D/A - 16 bit A/D,D/A - ± 10V@20mA excitation - ± 10V@20mA excitation Phases: Phases: 1. Filter input signal (sample every 1. Filter input signal (sample every 20 uSEC) 20 uSEC) 2. Check limits on input signal 2. Check limits on input signal if o.k. pass to phase 3 if o.k. pass to phase 3 3. Every 1mSEC send input signal to 3. Every 1mSEC send input signal to PID for control PID for control 4. Send control signal to “valve driver” 4. Send control signal to “valve driver”

19. windows LVDT LoadCell Filtering Setup of limits Limit check Master interlocks PID PV SP Rate Limiter ValveDriver return D/A A/D

20. Internal signal conditioner (LVDT) System Description: System Description: LVDT input: requires an excitation sine of 5KHz, 10V. LVDT output: amplitude modulated sine and sign (ΔΦ = 0 or 180 ) To find the position of the servo valve, the LVDT output is divided be the excitation, then filtered to get the correct DC value return

21. Valve driver Servo drive requirements : ±10V @ 70mA Servo drive requirements : ±10V @ 70mA PXI D/A spec: ±10V @ 20 mA. PXI D/A spec: ±10V @ 20 mA. The servo valve input requires a Bipolar excitation The servo valve input requires a Bipolar excitation (0 and π) (0 and π) The PXI 7831R synthesizes one vector, internal 16bit D/A drives the external power amplifier. The PXI 7831R synthesizes one vector, internal 16bit D/A drives the external power amplifier. The power amplifier generates the Bipolar signals The power amplifier generates the Bipolar signals Valve driver – power amp Specs: Valve driver – power amp Specs: – 2 x opa541 power operational amplifiers – +-15V supply, max current output 500mA – Output over load & temp protection – DC offset 5mV return returnreturn

22. conditioners LVDT: singer EL-15 series zero & gain trimmers zero & gain trimmers ±12V power supply ±12V power supply 10V, 5.7Khz sine excitation voltage 10V, 5.7Khz sine excitation voltage Load Cell: 10V DC excitation voltage 10V DC excitation voltage 12V power supply 12V power supply

23. Features summary Generic servo valve control system: suitable to general servo valves and conditioners configurations Generic servo valve control system: suitable to general servo valves and conditioners configurations Generic servo valve control system Generic servo valve control system Auto tune system: auto adjustments of control system parameters Auto tune system: auto adjustments of control system parameters Auto tune system Auto tune system Supports all required experiment waveforms Supports all required experiment waveforms Supports load and displacement control Supports load and displacement control Friendly GUI Friendly GUI Can be extended for additional waveforms, sensors, actuators and different GUI. Can be extended for additional waveforms, sensors, actuators and different GUI. Forward

24. Calibration and Manual tune Tuning and calibration is required After changing a part of the system (valve, sensors, ect..) return return return

25. Auto Tuning Different program was made for auto tuning. Different program was made for auto tuning. It finds the PID gains automatically for the servo valve, according to user requirements. It finds the PID gains automatically for the servo valve, according to user requirements. return

26. System Limitation (Bottlenecks) FPGA : FPGA : 1.Only 1M gates. (we use ~75% of it) 2.Long compile times for every change. 3.FPGA Emulator can’t simulate RT loops. LabVIEW Windows : LabVIEW Windows : 1. maximum time resolution of 1 ms. 2. Other programs running in the background may cause control gaps. may cause control gaps. possible solutions : possible solutions : 1.additional memory 1.additional memory 2.LabVIEW RT 2.LabVIEW RT

27. Future work Connect hydraulic and Hard interlocks to the FPGA. Connect hydraulic and Hard interlocks to the FPGA. integrate all Electronics and mechanical controls on to a suitable Enclosure. integrate all Electronics and mechanical controls on to a suitable Enclosure. Add data logging capabilities. Add data logging capabilities. Provide a client server function (web control). Provide a client server function (web control). Optional : Change execution environment from LabVIEW windows to LabVIEW’s RT module. Optional : Change execution environment from LabVIEW windows to LabVIEW’s RT module.

28. Demonstrations 1. Sine experiment LabVIEW 1. Sine experiment LabVIEW 2. Sine experiment Caliber 2. Sine experiment Caliber 3. Ramp experiment LabVIEW 3. Ramp experiment LabVIEW 4. Ramp experiment Caliber 4. Ramp experiment Caliber

29. THE END