Presentation is loading. Please wait.

Presentation is loading. Please wait.

Parallel–to-serial conversion(P712) 8.5 Shift Registers NextReturn serial input 8.5.1 Shift-Register Structure serial output parallel input parallel output.

Published by Modified over 8 years ago

Similar presentations

Presentation on theme: "Parallel–to-serial conversion(P712) 8.5 Shift Registers NextReturn serial input 8.5.1 Shift-Register Structure serial output parallel input parallel output."— Presentation transcript:

1 parallel–to-serial conversion(P712) 8.5 Shift Registers NextReturn serial input 8.5.1 Shift-Register Structure serial output parallel input parallel output serial-in, serial-out shift register (P712) serial-in, parallel -out shift register (P712) serial-to-parallel conversion(P712) parallel-in, serial-out shift register (P712)

2 gated clock 8.5 Shift Registers 8.5.2 MSI Shift Registers (P714~718) BackReturn serial input parallel output asynchronous clear input parallel input serial output asynchronous clear input Next

3 8.5 Shift Registers 8.5.2 MSI Shift Registers (74194 and 74299) parallel input parallel output asynchronous clear input bidirectional LIN QH HQH CLR GQG > CLK FQF S1 EQE S0 DQD G1 CQC G2 BQB AQA RIN QA parallel input parallel output(TS) asynchronous clear input bidirectional BackReturnNext

4 8.5 Shift Registers BackReturn 8.5.3 The World’s Biggest Shift-Register Application – Digital Telephony (P718) 8.5.4 * Serial/Parallel Conversion (P719~724) 8.5.5 Shift Register Counters (P724) 8.5.6 Ring Counters (P725~727) Simulation

Download ppt "Parallel–to-serial conversion(P712) 8.5 Shift Registers NextReturn serial input 8.5.1 Shift-Register Structure serial output parallel input parallel output."

Similar presentations

D Flip-Flop.

D Flip-Flop.
Shift Registers Module M11.1 Section 7.3.

Shift Registers Module M11.1 Section 7.3.
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.

Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
Half Adder Sum = X’Y+XY’ = X  Y Carry = XY YXYXYX  YYYX  XX XOR XNOR.

Half Adder Sum = X’Y+XY’ = X  Y Carry = XY YXYXYX  YYYX  XX XOR XNOR.
Ch 8. Sequential logic design practices 1. Documentation standards ▶ general requirements : signal name, logic symbol, schematic logic - state machine.

Ch 8. Sequential logic design practices 1. Documentation standards ▶ general requirements : signal name, logic symbol, schematic logic - state machine.
Shift Register Application Chapter 22 Subject: Digital System Year: 2009.

Shift Register Application Chapter 22 Subject: Digital System Year: 2009.
Digital Digital: Chapter 8. Sequential Logic Design Practices 1 Chapter 8. Sequential Logic Design Practices.

Digital Digital: Chapter 8. Sequential Logic Design Practices 1 Chapter 8. Sequential Logic Design Practices.
8.4 Counters NextReturn Any clocked sequential circuit whose state diagram contains a single cycle is called a counter. The number of states in the cycle.

8.4 Counters NextReturn Any clocked sequential circuit whose state diagram contains a single cycle is called a counter. The number of states in the cycle.
Simple Sequential Circuits in VHDL. Contents Sequential circuit examples: - SR latch in dataflow style - D flip-flop in behavioral style - shift register.

Simple Sequential Circuits in VHDL. Contents Sequential circuit examples: - SR latch in dataflow style - D flip-flop in behavioral style - shift register.
EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 22 Nov. 17, 2005 1.Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational.

EE42/100 Fall 2005 Prof. Fearing 1 Week 12/ Lecture 22 Nov. 17, Overview of Digital Systems 2.CMOS Inverter 3.CMOS Gates 4.Digital Logic 5.Combinational.
CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicJ: Counters José Nelson Amaral.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicJ: Counters José Nelson Amaral.
Shift Registers and Shift Register Counters

Shift Registers and Shift Register Counters
Shift Registers Lecture L6.6 Section 7.3. 4-Bit Shift Register.

Shift Registers Lecture L6.6 Section Bit Shift Register.
Sequential PLD timing Registers Counters Shift registers

Sequential PLD timing Registers Counters Shift registers
EET 1131 Unit 12 Shift Registers

EET 1131 Unit 12 Shift Registers
Digital Logic Design Lecture 24. Announcements Homework 8 due today Exam 3 on Tuesday, 11/25. – Topics for exam are up on the course webpage.

Digital Logic Design Lecture 24. Announcements Homework 8 due today Exam 3 on Tuesday, 11/25. – Topics for exam are up on the course webpage.
Registers and Shift Registers Discussion D8.2. D Flip-Flop 0 0 1 1 1 0 X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive.

Registers and Shift Registers Discussion D8.2. D Flip-Flop X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive.
Chapter 7 -- Modular Sequential Logic. Serial-in, Serial-out Shift Register.

Chapter 7 -- Modular Sequential Logic. Serial-in, Serial-out Shift Register.
Sistemas Digitais I LESI - 2º ano Lesson 8 - Sequential Design Practices U NIVERSIDADE DO M INHO E SCOLA DE E NGENHARIA Prof. João Miguel Fernandes

Sistemas Digitais I LESI - 2º ano Lesson 8 - Sequential Design Practices U NIVERSIDADE DO M INHO E SCOLA DE E NGENHARIA Prof. João Miguel Fernandes
1 EE365 More on sequential circuits. 2 Serial data systems (e.g., TPC)

1 EE365 More on sequential circuits. 2 Serial data systems (e.g., TPC)

Similar presentations

Ads by Google