1. P09311 Interface for Multipurpose Driver/ Data Acquisition System

2. Team Adam Van Fleet (EE) –DAQ Hardware Development –FPGA/DAQ Hardware Interface Development –Project Leader David Howe (EE) –DAQ Interfacing & USB Hardware Development –FPGA/DAQ Hardware Interface Development Michael Doroski (CE) –DAQ Interface Development (software) –Custom FPGA logic Thomas (TJ) Antonoff (CE) –USB interface development (software) Andrew Weida (CE) –FPGA Bluetooth interface development (UART) –GUI Development and PC Serial Communication

3. Customer Needs Customer Need #ImportanceDescriptionComments/Status CN1HighInterfaces DAQ to FPGA CN2HighInterfaces FPGA to PC CN3HighUtilizes USB interface CN4ModerateUtilizes Bluetooth Wireless interface CN5ModUSB Transfer rate minimum of 1.5Mbits/s and 12Mbits/sDepends on bottleneck limitations. CN6ModHighest possible Bluetooth transfer rateDepends on bottleneck limitations. CN7Low100% message transfer percentage (no lost packets) CN8HighCapable of transferring data CN9HighGUI - Connection settings available CN10HighGUI - Connection speed and status displayed CN11LowGUI - Displays GUI on Windows Operating System CN12HighGUI - Data Storage System CN13LowGUI – C# Programming LanguageNo restrictions on language. CN14ModInterchangeable FPGA'sDesign for 1, but needs to work for others. CN15LowVHDL programming languageChosen for portability, no restrictions on language. CN16High Meets all data production and transfer rates as specified for project P08311 CN17LowMultiple Bluetooth Connections an OptionMay disregard due to time constraints.

4. Project Specifications Engr. Spec. #ImportanceSource Specification (description) Unit of Measure Marginal ValueIdeal ValueComments/Status ES1MEDCN5 USB Transfer rate min of 1.5Mbits/s and max 12Mbits/sMb/s88 ES2MEDCN6 Bluetooth Transfer rate min 1.2 kb/s and max 921.6 kb/skb/s115921.6 ES3MEDCN7100% message transfer percentage (no lost packets)Packets0100% ES4LOWCN17Option for Multiple Bluetooth Connections# of modules33 ES5MEDCN4FPGA Programming LanguageLanguageVHDL ES6HIGHCN16Analog Data ResolutionBits12 ES7HIGHCN16Number of Analog Data ChannelsChannels16 ES8HIGHCN16Number of Digital Data ChannelsChannels12 ES9HIGHCN16Analog Sampling Rateksps20 Analog Input should be no more than 10 KHz ES10HIGHCN16Digital to Analog Data Supply RatekHz20 Analog Output will be updated at the same rate as input is taken ES11HIGHCN16Digital Sampling RateMHz10? As fast as necessary for ASIC ES12HIGHCN16Digital Data Supply RateMHz10? As Fast as necessary for ASIC

5. Project Features Feat. #ImportanceSource FeatureDescription F1HIGHCN8Capable of transferring data collected from the DAQ F2HIGHCN2Capable of Data Transfer between FPGA and PC F3HIGHCN9GUI – Connection settings available F4HIGHCN10GUI – Connection speed and status displayed F5HIGHCN11GUI – Displays GUI on Windows OS F6HIGHCN12GUI – Data storage system F7LOWCN13 GUI Programming Language C# F8MEDCN14 Ability to swap between FPGAs Allow for expansion

6. Hardware-Level System Overview RS-232 (921.6 kbps xfer) RS-232 USB Parani ESD210SK Bluetooth Dev. Kit Digilent Spartan-3 Board DLP-USB245M USB Adapter Windows-Based PC P08311 DAQ Board 64-pin (3.84 Mbps xfer) ASIC or Robotics Input 12-pin (up to 1.5 to 12MB/s xfer)

7. Pin-Outs for Additional Hardware 7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 5 6 First 30 pins from connector A2 Second 2 pins from connector A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O RD I/O WR TXE RXF DLP-USB245M Pins 13-24 are connected to FPGA pins 7 through 18 of connector A1

8. Data Flow Chart DAQFPGAPC `

9. Top Level: USB & Bluetooth Architecture Design DAQ FPGA USB Data Routing Logic USB FIFO USB Cable Bluetooth Modules Rx Tx Rx Tx RS232 1.2 - 230 kbps Bluetooth Wireless Serial PC 3.84 Mbps USB 8 Mbps Input Conditioning Output Conditioning Output Subsystem Input Subsystem UART 3.84 Mbps Control Unit

10. A/D Conversion on DAQ

11. D/A Conversion on DAQ

12. Overall Conversion Timing

13. Input Conditioning (Serial to Parallel Conversion) The purpose of this circuit is primarily converting from serial to parallel. This is done by shifting the serial analog data into the 12 bit shift registers. After 12 clock cycles, it is read out in parallel. The data then goes into a 48 to 24 mux with a 1 bit select line. The select line chooses whether to output the 24 bits of analog data or 12 bits of digital data prepended with 12 zeros. Thus, the multiplexer either outputs 24 bits of analog data or a total of 24 bits for digital data.

14. Output Conditioning (Parallel to Serial Conversion) This circuit functions similarly to the input conditioning circuit. A demultiplexer determines the destination of the data, either analog or digital. When analog is selected, the upper 12 bits is loaded in parallel to a 12 bit shift register while the lower 12 bits is loaded into a second 12 bit shift register. This data is then shifted out over 12 clock cycles to the DAQ for digital to analog conversion. If digital is selected, the front 12 bits are removed, since they will be zeros and the lower 12 bits are applied directly to the digital outputs.

15. Output Subsystem The output subsystem takes the data from input conditioning and prepackages it for transfer to the computer. This is done according to the state diagram on page 17.

16. Input Subsystem The input subsystem takes data deposited in the dual buffers on the right and prepares it for application to the DAQ. This is done according to the state diagram on page 18.

17. Custom Logic FSM State Diagrams Output Subsystem State Machine DataWriteEnReadEn Idle0000000000 Read240000000001 8 Bit Packet 1dddddddd10 8 Bit Packet 2dddddddd10 8 Bit Packet 3dddddddd10 Outputs

18. Input Subsystem State Machine DataWriteEnReadEn Idle000…000 PrepareToRead000…000 Read1stPacket000…001 Read2ndPacket000…001 Read3rdPacket000…001 ReassemblePackets000…000 WriteToDAQddd…d10 Custom Logic FSM State Diagrams Outputs

19. Dual Buffer Layout The Dual buffer circuit implements a ping pong scheme in order to eliminate problems with reading and writing at the same time. Basically, one FIFO is set to only be read and one is set to only be written to. When the writing buffer is full, the dualbuffer control switches the select signal for which FIFO is being written to. Thus, when the writing buffer is full, it switches with the reading buffer so that it can be emptied.

20. USB Design Logic

21. USB Read State Diagram StateTitleSignals (Output)Description 1IdleRD = 1, Write_EN = 0RXF buffer is empty or filling (less than 1 byte in USB RXF buffer) 2SendRD = 0, Write_EN = 1One byte of data sent in parallel to buffer on FPGA. 3ReloadRD = 1, Write_EN = 1Write acknowledge forces the USB buffer to load next byte into position for read. 4EmptyRD = 1, Write_EN = 0When USB RXF buffer empty, go back to idle state

22. USB Write State Diagram StateTitleSignals (Output)Description 1IDLERead_EN = 0, WR = 0FPGA buffer doesn’t have enough information to send to USB yet or USB buffer is full and needs to wait for space to be made. 2FPGA Read Read_EN = 1, WR = 1FPGA is ready to write to USB. Read_EN on FPGA is set high to start sending 1 byte to USB FIFO. 3USB WriteRead_EN = 1, WR = 0Once valid bit from FPGA is received, establishing proper data transfer from FPGA, USB device writes 1 byte to PC.

23. PinNameDirectionDescription 1CD«—Carrier Detect 2RXD«—Receive Data 3TXD—»Transmit Data 4DTR—» Data Terminal Ready 5GNDSystem Ground 6DSR«—Data Set Ready 7RTS—»Request to Send 8CTS«—Clear to Send 9RI«—Ring Indicator Hardware flow control is not supported on the connector. The port’s CD, DTR, and DSR signals connect together. Similarly, the port’s RTS and CTS signals connect together. The Parani-ESD has configurable hardware flow control. When hardware flow control is not being used, the Parani-ESD clears the buffer to secure room for the next data when the buffer becomes full. Loss of data may occur. As the transmission data becomes large, the possibility of data loss becomes greater. Spartan-3 Starter Board – RS232 Interface

24. SignalDescription CLKSystem Clock RSTAsynchronous active-high reset. Din[7:0]Eight-bits Data From Buffer LDLoad pulse to load Din in the Transmitter and start the transmission RxRS232 receive signal input. Is ’1’ when the line is idle. TxRS232 transmit signal output. Is ’1’ when the line is idle. Dout[7:0]Data received. RxRDYA ‘1’ pulse (one system clock cycle long) indicates that a character is received and is available at Dout. TxBusyIndicates that the UART is busy sending data. Will ignore any LD request. SDin[7:0] / SDout[7:0]Data received from RS-232 BuffDin[7:0] / BuffDout[7:0]Data From dual buffer, to be transmitted by UART WriteBuff / ReadBuffControl signal to write or read to/from Dual Buffer BuffFull / BuffEmptyIndicates if Buffers are Full or Empty. UART System

25. Write to UART Idle Read from Buffer Empty = 0 Underflow = 1ReadBuff = 1 LD_BuffDout = 1 Underflow = 0 Buffer to UART Empty = 1 TxBusy = 1 LD_BuffDout = 0 ReadBuff = 0 BuffDout[7:0] = BuffDin[7:0] TxBusy = 1

26. UART to Buffer Write to Buff Idle Read from UART BufffFull= 1 SDin[7:0] = Dout[7:0] Write_En = 1 BuffFull=0 Write_Ack = 1RxRDY= 0 RxRDY= 1 Write_Ack = 0 Write_En = 0

27. UART Transmit State Machine Idle Stop_tx Load_Tx Shift_Tx LD = 1 / Tx_Reg = Din & 1 TxBusy = 1 tx_tick = 1 / 0 tx_tick = 1 / Tx_Reg(0) = 0 TxBitCnt = 9 tx_tick = 1 / 0 TxBitCnt = 1 / 0 TxBitCnt > 1 / TxBitCnt = TxBitCnt – 1 Tx_Reg = 1 & Tx_Reg tx_tick = 0 / 0

28. UART Receive State Machine shift_rx stop_rx idle start_rx rx_ovf edge_rx Sample Data: -shift rx into a register -increment bit counter Here during stop bit rx_tick = 1 Rx_r = 0 rx_tick = 1 RxBitCnt = 8 rx_tick = 1 RxBitCnt < 8 Rx_d = 0 rx_tick = 1 Rx_r = 1 rx_tick = 1 Rx_r='1' Rx_d = 0 Rx_r = 0 Rx_r = 1 rx_tick = '1' Rx_r='1‘ rx_tick = 1 rx_tick = ‘0' Wait on Rx_d falling edge (start bit occurs) Framing error Wait on start bit: (Synchronize with rx_tick) Should be near Rx _d edge

29. Data Storage Format:,timestamp; GUIData Manager Control Signals Data Connection Info PC USB Cable PC Architecture Design (C#) Connection Handler Serial Cable Connection Media Connection Handler using System.IO.Ports: SerialPort Class

30. GUI Class Diagram

31. GUI Concept Design

32. Risk ItemLevelOwnerStatus and/or Contingency PlansDecision Date Transfer of knowledge from work of P08311 will be necessary for full system understanding LOWAdamMeet with Andrew Fitzgerald (P08311 Team Lead) to gather prior knowledge 10/3/08 Technological understanding of hardware / software to be used will be critical to success MEDAll Team Members Personal research / professional help will be requiredOngoing Transition from embedded processor may pose problems LOWAll Team Members Will require knowledge of P08311’s shortcomings10/17/08 Possibility for data transmission bottlenecks at FPGA interfaces CRITAdam, Andrew, TJ, Dave Develop alternative method for data transmission (multiple devices in parallel, controlling the DAQ clock speed, etc.) 10/17/08 No background in Bluetooth or USB; interface will require considerable time to produce MEDAdam, Andrew, TJ, Dave Extensive research of modes of data transfer will be requiredEnd of Quarter Shortcomings of P08311’s work (Compact flash memory, embedded PowerPC processor, etc.) will need to be evaluated LOWAll Team Members Research into previous data bottlenecks and possible solutions10/17/08 Interfacing FPGA to DAQ without any I/O expansion will pose a problem (Spartan-3 board) MEDAdam, DaveResearch of FPGA’s containing enough I/O’s to handle all inputs/outputs from the DAQ board 10/17/08 Interfacing FPGA to Bluetooth / USB without any I/O expansion will pose a problem (Spartan-3 board) LOWAdam, DaveResearch of FPGA’s containing enough I/O’s to handle all inputs/outputs from the DAQ board 10/17/08 VHDL knowledge (3 members have basic knowledge, 2 members have almost no knowledge) MEDAll Team Members All team members will need to educate themselves in this area, as majority of software side of project revolves around VHDL End of Quarter Accurate monitoring of connection speed and status via GUI LOWAndrew, MikeDecrease refresh rate to allow for better calculationEnd of Quarter Risk Assessment

33. Appendix Spartan-3 Board Reference Material http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&N av2=Programmable DLP-USB245M USB Adapter http://www.dlpdesign.com/usb/usb245.shtml Parani ESD210SK Bluetooth Dev. Kit http://www.rfphone.com/files/ESD110.pdf Digital to Analog Converter http://www.analog.com/static/imported-files/data_sheets/AD5308_5318_5328.pdf Analog to Digital Converter http://cache.national.com/ds/DC/ADC121S101.pdf