1. Rajeev K. Ranjan Advanced Technology Group Synopsys Inc. Using Combinational Verification for Sequential Circuits Joint work with: Vigyan Singhal, Cadence Berkeley Labs, Berkeley Fabio Somenzi, Univ. of Colorado, Boulder Robert K. Brayton, Univ. of California, Berkeley

2. Rajeev K. Ranjan Advanced Technology Group Synopsys Inc. Using Combinational Verification with Sequential Optimization Joint work with: Vigyan Singhal, Cadence Berkeley Labs, Berkeley Fabio Somenzi, Univ. of Colorado, Boulder Robert K. Brayton, Univ. of California, Berkeley

3. Motivation High complexity of sequential circuit verification Very little sequential optimization performed due to lack of practical verification tool Significant advancements in combinational verification domain - commercial tools, part of design flow BUT Large gap in combinational vs. sequential optimization capability Leverage the gap between sequential and combinational optimization

4. Our Work Restricted sequential optimization IIterative synthesis and retiming Constraint on the retiming transformation Verification complexity EExtension of combination verification problem Proposed Optimization Capability Verification Complexity Combinational Sequential

5. Previous Work: General Sequential Equivalence State space exploration based techniques  Requires state-space traversal of product machine  Explicit search (DDHY92)  Implicit search (CBM89, BCML90)  State-space explosion problem ATPG based:  AQUILA (HCC97)  Relies on finding equivalent points  symbolic justification procedure

6. Previous Work: Equivalence with Constrained Optimization HCC96: Verification of retimed circuits.  Relies on finding correspondence of flip-flops AGM96: Verification of “complete-1-distinguishable” circuits.  Requires state-space traversal of individual machines. SK97, E98: Structural technique  Relies on finding logic transformations  Solves a series of combinational equivalence problem

7. Related Work: Bischoff et al. (ICCD 97) Compared RTL with gates extracted from a custom transistor netlist “Retiming comparison” used to compare logic across flip-flop boundaries No formal framework for such verification presented No technique given to handle circuits with feedback paths

8. Outline Background Sequential circuit without feedback  Circuits with regular flip-flops  Circuits with enabled flip-flops Sequential circuit with feedback Experimental results Conclusion

9. Background: Sequential Circuit Gates and memory elements Edge triggered Enable signal Single global clock e

10. Background: Combinational Synthesis Primary InputsPrimary Outputs Flip-flop InputsFlip-flop Outputs

11. Background: Retiming [Leiserson & Saxe] Retime by +1 Retime by -1

12. Iterative Retiming and Resynthesis: (T + S) * Retiming changes interaction between different combinational blocks Combinational synthesis generates new candidate flip-flop locations Sequence of retiming and synthesis provides powerful sequential optimization technique

13. Main Idea Create an acyclic representation of the circuit  Restrict retiming of some flip-flops if needed Perform iterative retiming and resynthesis Obtain combinational representations for original and optimized circuit and perform combinational equivalence Notion of equivalence: Steady-state Ignores the transient behavior (initialization of flip-flops) Compares the steady-state behavior

14. Sequential Circuit without Feedback Circuits with regular flip-flops  Outputs dependent on inputs at multiple time instants  Time instants defined by clock ticks  e.g. (t-1) indicates one clock tick ago  Clocked Boolean Function (CBF) Circuits with load-enabled flip-flops  Outputs dependent on inputs at multiple time instants  Time instants defined by the events  e.g.  (e) indicates latest time at which “e” was true  Event Driven Boolean Function (EDBF)

15. Clocked Boolean Function (CBF) sy s(t) = y(t-1) s : Primary input s(t) primary input ststtt()('),'  Combinational representation of acyclic sequential circuit with regular flip-flops. F y1y1 y2y2 ymym s s(t) = F( y 1 (t), y 2 (t), …, y m (t))

16. Clocked Boolean Function: Illustration ab cd o otctdt()()()  dtct()()  1 ctbtat()()()  btat()()  1 otatatatat()(()())(()(  121 CBF captures the steady-state value of the outputs

17. Clocked Boolean Function: Illustration ab cd o Original circuit Combinational representation a(t) c d o a(t-1) a(t-2)

18. Canonicity of CBF Theorem: C 1 and C 2 are two acyclic sequential circuits F 1 and F 2 their CBFs, then FFCC 1212 

19. Event Driven Boolean Function (EDBF) Combinational representation of acyclic sequential circuit with load-enabled flip-flops. F y1y1 y2y2 ymym s sEfyEyEyE m (())((()),((...,(()))  12 sy e sEyeE(())(([])  s : Primary input primary input sEsEEE(())((')),'  sE(()) 

20. EDBF: Illustration ab cd o e1e1 e2e2 odc([])( (   dce( ([])  2 cab([])( (   bae( ([])  1 oaaeaeaee([])(( ([]))(([])([]))     1112 EDBF captures the steady-state value of the outputs

21. EDBF: Illustration ab cd o c d o Original circuit Combinational representation e1e1 e2e2 ae([])  1 aee([  12 a([]) 

22. Canonicity of EDBF Theorem: u C 1 and C 2 (obtained from C1 by retiming and synthesis) are two acyclic sequential circuits u F 1 and F 2 their EDBFs, then FFCC 1212 

23. Synthesis does not change functionality Retiming = (Basic retiming) * Basic retiming results in equivalent EDBFs By transitivity result holds for Iterative retiming moves across primitive elements Canonicity of EDBF (proof):

24. Sequential Circuit with Feedback C1 C2 x e d Key idea: Model feedback path with a flip-flop fed by a multiplexer. e d e d Model direct feedback path to a flip-flop with load enabled flip-flop e d C2 No feedback path

25. Modeling Feedback Path: Decomposition Condition x : Output signal of a flip-flop with feedback path F(x) : Next state function of the flip-flop, then FxedexFF xx ()  FdF eFF xx xx   i.e., F(x) should be positive unate in x Conditions on data and enable signal: e is a function of primary inputs only

26. Methodology: Summary Expose the (designer specified) registers which cannot be retimed If the resulting circuit is acyclic, continue If the next state function of each flip-flop with a feedback path is positive unate, perform appropriate modeling, continue If not, expose minimum number of flip-flops to make it acyclic, continue

27. Experimental Setup Circuit modification: Identify minimal set of flip-flops to expose to make the circuit acyclic Combination optimization: SIS with modified version of “script.delay” Retiming: Using MINARET (MS97)  Minimum area for delay obtained by combinational optimization  Minimum area for minimum feasible period CBF equivalence mapped onto combinational equivalence

28. Experimental Results Combinational optimization. Retiming and resynthesis.

29. Conclusion Practical retiming and resynthesis based sequential optimization and verification methodology Constraint on the feedback path (if one exists) of flip- flops being retimed Constraints can be met by exposing some flip-flops Faster circuits using retiming with reasonable verification time Availability of retiming tool capable of moving enabled flip-flops critical