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Embedded Computing From Theory to Practice November 2008 USTC Suzhou.

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Presentation on theme: "Embedded Computing From Theory to Practice November 2008 USTC Suzhou."— Presentation transcript:

1 Embedded Computing From Theory to Practice November 2008 USTC Suzhou

2 11/2008© Xiaoning Nie2 FAQs  How useful is theory in practice?  How hard is reality ?  Some example to illustrate what way of thinking is expected in practice.

3 11/2008© Xiaoning Nie3 Embedded Systems  Specific applications –Communications: mobile phone, DSL home gateway –Automotive: engine & brake control, … –Consumer, Aerospace, Medical …  Embedded computing hardware –EDA tools –Performance, cost, power, size  Embedded software –Correct functions and realtime-ness –Performance, cost, power

4 11/2008© Xiaoning Nie4 Example 1: Automotive Trend

5 11/2008© Xiaoning Nie5 Example 2: Mobile Phone Trend

6 11/2008© Xiaoning Nie6 Very Large Integration Trend

7 11/2008© Xiaoning Nie7 Computing Architecture Trend  Intel Tera-Scale architecture with 80 Cores * Intel Technology Journal Issue 3, 2007

8 11/2008© Xiaoning Nie8 Theory & Practice A Hardware Case

9 11/2008© Xiaoning Nie9 Hardware fundamentals  Processor architecture –RISC: 16bit, 32bit, 64bit –Pipeline: for high clock frequency –Cache: L1, L2, etc  Memory  Bus & IO  Accelerator Embedded Computing Platform

10 11/2008© Xiaoning Nie10 Processor performance  MIPS = Million Instructions Per Second –Important measure of CPU performance  Theory –RISC processor –IPC: One instruction per cycle  IPC = 1.0 –Clock frequency F = 100 MHz  MIPS = F * IPC = 100

11 11/2008© Xiaoning Nie11 Design practice ( I )  Application –Run code and measure instructions executed –Assume 1000 M I P S  Taking 2 x 500 MHz ARM core ? –10 % branches: 3 x 100 Mio cycles –20 % load/store: 10 x 200 Mio cycles  Additional MHz needed –2 x 100 MHz for branches –9 x 200 MHz for loads/stores

12 11/2008© Xiaoning Nie12 Design practice ( II )  Add 4 x 500 MHz cores. IPC = ?  How can I get in all the instructions ? –1000 M I P S –Bus / DRAM clock: 266 MHz –Instruction words 266 per second –Solution 4 x width = 128 bit  To consider inst. reuse and cache miss –more than 1000 Mio. instructions per second  All these need to be considered in your design.

13 11/2008© Xiaoning Nie13 Theory & Practice A Software Case

14 11/2008© Xiaoning Nie14 Programming fundamentals  Data structure –Array e.g. int a[100], b[100]; –Pointer e.g. int *p = malloc( 100*sizeof(int) ); –Linked list struct list { list *pre; list *suc; int member;} *mylist;

15 11/2008© Xiaoning Nie15 Software design practice ( I )  What does malloc( ) do ? –System dependent –Library function of OS –May differ 1000% in performance

16 11/2008© Xiaoning Nie16 Software design practice ( II )  Data assignment for (i=0; i<100; i++) a[i] = b[i] ;  How many memory accesses? –0? –100 ? –200 ?  Impact on –speed and power consumption

17 11/2008© Xiaoning Nie17 Software design practice ( III )  Data assignment for (i=0; i member; mylist = mylist -> suc; }  How many memory accesses? –100 ? –200 ? –300 ? ….

18 11/2008© Xiaoning Nie18 Conclusions  Examples from real project  Way of thinking –I have a solution. –I have a working solution. –I have a optimally working solution.  The latter is paid more


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