1. ECE 667 - Synthesis & Verification - Lecture 0 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Boolean Functions and Circuits Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003

2. module example(clk, a, b, c, d, f, g, h) input clk, a, b, c, d, e, f; output g, h; reg g, h; always @(posedge clk) begin g = a | b; if (d) begin if (c) h = a&~h; else h = b; if (f) g = c; else a^b; end else if (c) h = 1; else h ^b; end endmodule Specification d a b e f c 0 h g clk Logic Extraction Synthesis Flow a multi-stage process Technology-Independent Optimization f g0 h1 a c e g1 h3 h5 H G b d Technology-Dependent Mapping f d b e a c clk h H G g

4. ECE 667 - Synthesis & Verification - Lecture 0 4 What is Logic Synthesis? D XY Given:Finite-State Machine F(X,Y,Z,, ) where: X: Input alphabet Y: Output alphabet Z: Set of internal states : X x Z Z (next state function, Boolean) : X x Z Y (output function, Boolean) Target:Circuit C(G, W) where: G: set of circuit components  g {Boolean gates, flip-flops, etc} W: set of wires connecting G

5. ECE 667 - Synthesis & Verification - Lecture 0 5 The Boolean Space B n B = { 0,1}, B 2 = {0,1} X {0,1} = {00, 01, 10, 11} B0B0B0B0 B1B1B1B1 B2B2B2B2 Karnaugh Maps:Boolean Cubes: B3B3B3B3 B4B4B4B4

6. ECE 667 - Synthesis & Verification - Lecture 0 6 Boolean Functions x2x2 x1x1

7. ECE 667 - Synthesis & Verification - Lecture 0 7 Boolean Functions Literal x 1 represents the logic function f, where f = {x| x 1 = 1} Literal x 1 represents the logic function g where g = {x| x 1 = 0} x1x1 x3x3 x2x2 f = x 1 x1x1 x2x2 x3x3 Notation: x’ = x

8. ECE 667 - Synthesis & Verification - Lecture 0 8 Set of Boolean Functions There are 2 n vertices in input space B n There are 2 2 n distinct logic functions. – –Each subset of vertices is a distinct logic function: f  B n x 1 x 2 x 3 0 0 0 1 0 0 1 0 0 1 0 1 1 0 1 0 0  1 1 0 1 1 0 1 1 1 1 0 x1x1 x2x2 x3x3 Truth Table or Function Table :

9. ECE 667 - Synthesis & Verification - Lecture 0 9 Boolean Operations - AND, OR, COMPLEMENT Given two Boolean functions : f : B n  B g : B n  B The AND operation h = f  g is defined as h = {x | f(x)=1  g(x)=1} The OR operation h = f  g is defined as h = {x | f(x)=1  g(x)=1} The COMPLEMENT operation h = ^f (or f’ ) is defined as h = {x | f(x) = 0}

10. ECE 667 - Synthesis & Verification - Lecture 0 10 Cofactor and Quantification Given a Boolean function: f : B n  B, with the input variables (x 1,x 2,…,x i,…,x n ) The Positive Cofactor h = f xi is defined as h = {x | f(x 1,x 2,…,1,…,x n )=1} The Negative Cofactor h = f xi is defined as h = {x | f(x 1,x 2,…,0,…,x n )=1} The Existential Quantification of function h w.r.t variable x i, h =  x i f is: h = {x | f(x 1,x 2,…,0,…,x n )=1  f(x 1,x 2,…,1,…,x n )=1} The Universal Quantification of function h w.r.t variable x i, h =  x i f is: h = {x | f(x 1,x 2,…,0,…,x n )=1  f(x 1,x 2,…,1,…,x n )=1}

11. ECE 667 - Synthesis & Verification - Lecture 0 11 Representation of Boolean Functions We need representations for Boolean Functions for two reasons: – –to represent and manipulate the actual circuit we are “synthesizing” – –as mechanism to do efficient Boolean reasoning Forms to represent Boolean Functions – –Truth table – –List of cubes: Sum of Products, Disjunctive Normal Form (DNF) – –List of conjuncts: Product of Sums, Conjunctive Normal Form (CNF) – –Boolean formula – –Binary Decision Tree, Binary Decision Diagram – –Circuit (network of Boolean primitives) Canonicity – which forms are canonical?

12. ECE 667 - Synthesis & Verification - Lecture 0 12 Truth Table Truth table (Function Table):Truth table (Function Table): The truth table of a function f : B n  B is a tabulation of its values at each of the 2 n vertices of B n. (all mintems) Example: f = a’b’c’d + a’b’cd + a’bc’d + ab’c’d + ab’cd + abc’d + abcd’ + abcd (Notation for complement: a’ = a ) The truth table representation is - intractable for large n - canonical Canonical means that if two functions are the same, then the canonical representations of each are isomorphic (identical). abcd f 0 0000 0 1 0001 1 2 0010 0 3 0011 1 4 0100 0 5 0101 1 6 0110 0 7 0111 0 8 1000 0 9 1001 1 10 1010 0 11 1011 1 12 1100 0 13 1101 1 14 1110 1 15 1111 1

13. ECE 667 - Synthesis & Verification - Lecture 0 13 Boolean Formula A Boolean formula is defined as an expression with the following syntax: formula ::= ‘(‘ formula ‘)’ | |formula “+” formula(OR operator) |formula “  ” formula(AND operator) | ^ formula(complement) Example: f = (x 1  x 2 ) + (x 3 ) + ^^(x 4  (^x 1 )) typically the “  ” is omitted and the ‘(‘ and ‘^’ are simply reduced by priority, e.g. f = x 1 x 2 + x 3 + x 4 ^x 1

14. ECE 667 - Synthesis & Verification - Lecture 0 14 Cubes A cube is defined as the product (AND) of a set of literal functions (“conjunction” of literals). Example: C = x 1 x’ 2 x 3 represents the following function f = (x 1 =1)(x 2 =0)(x 3 =1) x1x1 x2x2 x3x3 c = x 1 x1x1 x2x2 x3x3 f = x 1 x 2 x1x1 x2x2 x3x3 f = x 1 x 2 x 3

15. ECE 667 - Synthesis & Verification - Lecture 0 15 Cubes If C  f, C a cube, then C is an implicant of f. If C  B n, and C has k literals, then |C| covers 2 n-k vertices. Example: C = xy  B 3 k = 2, n = 3 => |C| = 2 = 2 3-2. C = {100, 101} In an n-dimensional Boolean space B n, an implicant with n literals is a minterm.

16. ECE 667 - Synthesis & Verification - Lecture 0 16 List of Cubes Sum of Products (SOP) A function can be represented by a sum of cubes (products): f = ab + ac + bc Since each cube is a product of literals, this is a “sum of products” (SOP) representation A SOP can be thought of as a set of cubes F F = {ab, ac, bc} A set of cubes that represents f is called a cover of f. F 1 ={ab, ac, bc} and F 2 ={abc, abc, abc, abc} are covers of f = ab + ac + bc.

17. ECE 667 - Synthesis & Verification - Lecture 0 17 Binary Decision Diagram (BDD) f = ab+a’c+a’bd 1 0 c a bb cc d 0 1 c+bd b root node c+d d Graph representation of a Boolean function - vertices represent decision nodes for variables - two children represent the two subfunctions f(x = 0) and f(x = 1) (cofactors) - restrictions on ordering and reduction rules can make a BDD representation canonical

18. ECE 667 - Synthesis & Verification - Lecture 0 18 Boolean Circuits (Networks) Used for two main purposes – –as representation for Boolean reasoning engine – –as target structure for logic implementation which gets restructured in a series of logic synthesis steps until result is acceptable Efficient representation for most Boolean problems we have in CAD – –memory complexity is same as the size of circuits we are actually building Close to input representation and output representation in logic synthesis

19. ECE 667 - Synthesis & Verification - Lecture 0 19 Definitions – fanin, fanout, support Definition: A Boolean circuit is a directed graph C(G,N) where G are the gates and N  G  G is the set of directed edges (nets) connecting the gates. Some of the vertices are designated: Inputs: I  G Outputs: O  G, I  O =  Each gate g is assigned a Boolean function f g which computes the output of the gate in terms of its inputs.

20. ECE 667 - Synthesis & Verification - Lecture 0 20 Definitions – fanin, fanout, support The fanin FI(g) of a gate g are all predecessor vertices of g: FI(g) = {g’ | (g’,g)  N} The fanout FO(g) of a gate g are all successor vertices of g: FO(g) = {g’ | (g,g’)  N} The cone CONE(g) of a gate g is the transitive fanin of g and g itself. The support SUPPORT(g) of a gate g are all inputs in its cone: SUPPORT(g) = CONE(g)  I

21. ECE 667 - Synthesis & Verification - Lecture 0 21 Example – Boolean network I O FI(6) = {2,4} FO(6) = {7,9} CONE(6) = {1,2,4,6} SUPPORT(6) = {1,2} 6 1 5 3 4 7 8 9 2

22. ECE 667 - Synthesis & Verification - Lecture 0 22 Circuit Function Circuit functions are defined recursively: If G is implemented using physical gates that have positive (bounded) delays for their evaluation, the computation of h g depends in general on those delays. Definition: A circuit C is called combinational if for each input assignment of C for t  the evaluation of h g for all outputs is independent of the internal state of C. Proposition: A circuit C is combinational if it is acyclic.

23. ECE 667 - Synthesis & Verification - Lecture 0 23 SAT and Tautology Tautology: – –Find an assignment to the inputs that evaluate a given vertex to “0”. SAT : – –Find an assignment to the inputs that evaluate a given vertex to “1”. – –Identical to Tautology on the inverted vertex SAT on circuits is identical to the justification part in ATPG – –First half of ATPG: justify a particular circuit vertex to “1” – –Second half of ATPG (propagate a potential change to an output) can be easily formulated as SAT (will be covered later) – –Basic SAT algorithms: – –branch and bound algorithm as seen before branching on the assignments of primary inputs only (Podem algorithm) branching on the assignments of all vertices (more efficient)

24. ECE 667 - Synthesis & Verification - Lecture 0 24 Circuit Representations For general circuit manipulation (e.g. synthesis): Vertices have an arbitrary number of inputs and outputs Vertices can represent any Boolean function stored in different ways, such as: – –other circuits (hierarchical representation) – –Truth tables or cube representation (e.g. SIS system) – –Boolean expressions read from a library description – –BDDs (e.g BDS system) Data structure allow very general mechanisms for insertion and deletion of vertices, pins (connections to vertices), and nets – –general but far too slow for Boolean reasoning

25. ECE 667 - Synthesis & Verification - Lecture 0 25 Circuit Representations For efficient Boolean reasoning (e.g. a SAT engine): Circuits are non-canonical – –computational effort is in the “checking part” of the reasoning engine (in contrast to BDDs) Vertices have fixed number of inputs (e.g. two) Vertex function is stored as label, well defined set of possible function labels (e.g. OR, AND,OR) on-the-fly compaction of circuit structure – –allows incremental, subsequent reasoning on multiple problems

26. ECE 667 - Synthesis & Verification - Lecture 0 26 Boolean Reasoning Engine Engine Interface: void INIT() void QUIT() Edge VAR() Edge AND(Edge p1, Edge p2) Edge NOT(Edge p1) Edge OR(Edge p1 Edge p2)... int SAT(Edge p1) Engine application : - traverse problem data structure and build Boolean problem using the interface - call SAT to make decision Engine Implementation:... External reference pointers attached to application data structures

27. ECE 667 - Synthesis & Verification - Lecture 0 27 Basic Approaches Boolean reasoning engines need:Boolean reasoning engines need: –a mechanism to build a data structure that represents the problem –a decision procedure to decide about SAT or UNSAT Fundamental trade-offFundamental trade-off –canonical data structure data structure uniquely represents functiondata structure uniquely represents function decision procedure is trivial (e.g., just pointer comparison)decision procedure is trivial (e.g., just pointer comparison) example: Reduced Ordered Binary Decision Diagramsexample: Reduced Ordered Binary Decision Diagrams Problem: Size of data structure is in general exponentialProblem: Size of data structure is in general exponential –non-canonical data structure systematic search for satisfying assignmentsystematic search for satisfying assignment size of data structure is linearsize of data structure is linear Problem: decision may take an exponential amount of timeProblem: decision may take an exponential amount of time

28. ECE 667 - Synthesis & Verification - Lecture 0 28 AND-INVERTER Circuits Base data structure uses two-input AND function for vertices and INVERTER attributes at the edges (individual bit) – –use De’Morgan’s law to convert OR operation etc. Hash table to identify and reuse structurally isomorphic circuits f g g f Means complement

29. ECE 667 - Synthesis & Verification - Lecture 0 29 Data Representation Vertex : – –pointers (integer indices) to left and right child and fanout vertices – –collision chain pointer – –other data Edge: – –pointer or index into array – –one bit to represent inversion Global hash table holds each vertex to identify isomorphic structures Garbage collection to regularly free un-referenced vertices

30. ECE 667 - Synthesis & Verification - Lecture 0 30 Data Representation 0456 left right next fanout 1345 …. 8456 …. 6423 …. 7463 …. 0 1 hash value left pointer right pointer next in collision chain array of fanout pointers complement bits Constant One Vertex zero one 0456 0455 0457... Hash Table 0456 left right next fanout 0 0

31. ECE 667 - Synthesis & Verification - Lecture 0 31 Hash Table Algorithm HASH_LOOKUP(Edge p1, Edge p2) { index = HASH_FUNCTION(p1,p2) p = &hash_table[index] while(p != NULL) { if(p->left == p1 && p->right == p2) return p; p = p->next; } return NULL; } Tricks: - keep collision chain sorted by the address (or index) of p - that reduces the search through the list by 1/2 - use memory locations (or array indices) in topological order of circuit - that results in better cache performance

32. ECE 667 - Synthesis & Verification - Lecture 0 32 Basic Construction Operations Algorithm AND(Edge p1,Edge p2){ if(p1 == const1) return p2 if(p2 == const1) return p1 if(p1 == p2) return p1 if(p1 == ^p2) return const0 if(p1 == const0 || p2 == const0) return const0 if(RANK(p1) > RANK(p2)) SWAP(p1,p2) if((p = HASH_LOOKUP(p1,p2)) return p return CREATE_AND_VERTEX(p1,p2); }

33. ECE 667 - Synthesis & Verification - Lecture 0 33 Basic Construction Operations Algorithm OR(Edge p1,Edge p2){ return (NOT(AND(NOT(p1),NOT(p2)))) } Algorithm NOT(Edge p) { return TOOGLE_COMPLEMENT_BIT(p) }

34. ECE 667 - Synthesis & Verification - Lecture 0 34 Cofactor Operation Algorithm POSITIVE_COFACTOR(Edge p,Edge v){ if((c = GET_COFACTOR(p)) == NULL) { if(p == v) { if(IS_INVERTED(v)) return const0 else return const1 } left = POSITIVE_COFACTOR(p->left, v) right = POSITIVE_COFACTOR(p->right, v) if(IS_INVERTED(p)) return NOT(AND(left,right)) else return AND(left,right) SET_COFACTOR(p,c); } return c; } - similar algorithm for NEGATIVE_COFACTOR - existential and universal quantification build from AND, OR and COFACTORS Question: What is the complexity of the circuits resulting from quantification?