1. CSE241 VLSI Digital Circuits Winter 2003 Lecture 15: Packaging

2. Topics
Packaging IO
Pads
Bumps
Area vs. peripheral IO

3. Packaging Styles Popular Package Materials: Flip-chip BGA TSOP Ceramic
Plastic

4. Die Connections Pads 1 row: 70µ pitch 2 rows: 40-50µ staggered pitch
Logic devices – Around periphery of die
1 row: 70µ pitch
2 rows: 40-50µ staggered pitch
Memory (DRAM) – in a line at center of die
1 row: µ pitch

5. Flip-chip Entire surface of die can be covered with bonding sites
Placed on 250µ centers
Small balls (bumps) added at wafer level
Chip flipped over and connected to package
Substrate is at top of package
Slide courtesy of Stanford

6. Package Styles Logic Memory BGA QFP TSOP CSP Ball Grid Array
Quad Flat Pack
Memory
TSOP
Thin Small Outline Package
CSP
Chip Scale Package

7. Other Packages Types CDIP Ceramic Dual In-Line Pkg SB Side-Braze
PFM Plastic Flange Mount Pkg
PLCC Plastic Leaded Chip Carrier
PPGA Plastic Pin Grid Array
QFP Quad Flat Pkg.
SDIP Shrink Dual-I-Line Pkg
SIP Single-In-Line Pkg.
SOJ J-Leaded Small-Outline Pkg
SOP Small-Outline Pkg
Triple Flat PackTO/SOT Cylindrical Pkg
TSOP Thin Small-Outline Pkg.
TSSOP Thin Shrink Small-Outline Pkg
VFLGA Thin Very-Fine Land Grid Array
TVSOP Very Thin Small-Outline Pkg
VQFP Very Thin Quad Flat Pkg
VSOP Very Small Outline Pkg
CDIP Ceramic Dual In-Line Pkg
SB Side-Braze
CPGA Ceramic Pin Grid Array
CZIP Ceramic Zig-Zag Pkg
DFP Dual Flat Pkg
HLQFP Thermally Enhanced Low Profile
LCC J-Leaded Ceramic or Metal Chip Carrier
LCCC Leadless Ceramic Chip Carrier
LGA Land Grid Array
LPCC Leadless Plastic Chip Carrier
LQFP Low Profile Quad Flat Pack
MCM Multi-Chip Module
MQFP Metal Quad Flat Pkg
PDIP Plastic Dual-In-Line Pkg

8. Ball Grid Array Pin Counts Clock Frequency 450 2116 2.5GHz
MHz
MHz
MHz
MHz
MHz
FC-BGA
TAB-BGA
EBGA
FDH-BGA
PBGA
FBGA
Slide courtesy of Fujitsu

9. TSOP Thin Small Outline Package (TSOP) Most popular DRAM package
Very cheap
Wires bond to lead frame
Bond pads sometimes at center of die
Leaded surface mount
Photo courtesy of Stanford

10. BGA Ball Grid Array Most popular ASIC package
Basically a small printed circuit board
Multiple planes available in package
Possible to route larger numbers of signals
Better signal integrity
Photo courtesy of Stanford

11. QFP Wire Bond package Leads are coplanar fanning into die
Higher coupling
Photo courtesy of Fujitsu

12. Packaging Trends Memory: Logic Stacked die
Higher density (3-D scaling)
Still uses same inexpensive die
Logic

13. I/Os I/O Drivers Backwards compatibility a key problem
I/O driver design is always challenging
Backwards compatibility a key problem
Core Supply voltages changing
Older devices will have larger swings than new ones
Old: TTL level
Modern: 1.5v, 2.0v
Bandwidth requirements increasing
Need to have more pins or higher bandwidth per pin or both
Memory interface widths
Encryption keys

14. I/O Pads Traditional Flip-chip ESD Pads at periphery
Pads anywhere on die
ESD
Provide Esd protection to die
Human model
Models capacitive discharge from handling

15. Pads Types Generic: Analog Memory High-speed High-voltage Input/output
Bi-directional
Tri-state
Analog
Differential
Memory
High-speed
>1Ghz
High-voltage
>5v

16. Bumps Flip-chip Advantages Power (Vdd/Vss) Signals Power:
Are locally fed
Reduces skew
Reduces delay of pushing to chip boundary
Power:
Local power
Multiple Vdd sources
Different Vdd