2. General Purpose Processors: Software

3. This Week In DIG II  Introduction  Basic Architecture  Operation  Programmer’s view (that would be you !)  Development environment  Application specific instruction-Set Processors (ASIPs)  Selecting a microprocessor  Z-World  General – purpose processor design Chapter 3 General-Purpose Processors: Software

4. Introduction  General-Purpose Processor  Processor designed for a variety of computation tasks  Low unit cost, in part because manufacturer spreads NRE over large numbers of units Motorola sold half a billion 68HC05 microcontrollers in 1996 alone  Carefully designed since higher NRE is acceptable Can yield good performance, size and power  Hand picked, top-notch designers (you!)  Low NRE cost for embedded system manufacturer, short time-to- market/prototype, high flexibility User just writes software; no processor design  a.k.a. “microprocessor” – “micro” used when they were implemented on one or a few chips rather than entire rooms

5. Basic Architecture  Control unit and datapath  Note similarity to single- purpose processor  Key differences  Datapath is general  Control unit doesn’t store the algorithm – the algorithm is “programmed” into the memory Processor (CPU) Control unit Datapath ALU Registers IRPC Controller Memory I/O Control /Status

6. Datapath Operations LL oad RR ead memory location into register AA LU operation II nput certain registers through ALU, store back in register SS tore WW rite register to memory location Processor Control unitDatapath ALU IRPC Controller Memory I/O Control /Status 10... 10 +1 11 Registers Datapath: transform data and store temporary data

7. Control Unit CC ontrol unit: configures the datapath operations RR etrieve program instructions MM ove data to, from and through the datapath according to these instructions SS equence of desired operations (“instructions”) stored in memory – “program” CC ontrol unit consists of PP rogram counter: II nstruction register: CC ontroller: PP C’s bit-width determines the processor’s address size: 16-bit PC can address 2 16 (65,536) directly accessible memory locations. Processor Control unitDatapath ALU Registers IRPC Controller Memory I/O Control /Status 10... load R0, M[500] 500 501 100 inc R1, R0 101 store M[501], R1 102 R0R1

8. Controller  What does the controller really do?…you ask…  Controller sequences through several stages:  Instruction cycle – broken into several sub-operations, each one clock cycle, e.g.:  Fetch  Decode  Fetch operands  Execute  Store results

9. Control Unit Sub-Operations  Fetch  Get next instruction into IR  PC: program counter, always points to next instruction  IR: holds the fetched instruction  Decode  Determine what the instruction means Processor Control unit Datapath ALU Registers PC Controller Memory I/O Control /Status 10... load R0, M[500] 500 501 100 inc R1, R0 101 store M[501], R1 102 R0R1100 load R0, M[500] IR

10. Control Unit Sub-Operations  Fetch operands  Move data from memory to datapath register  Execute  Move data through the ALU  This particular instruction does nothing during this sub- operation  Store results  Write data from register to memory Processor Control unitDatapath Registers PC Controller Memory I/O Control /Status 10... load R0, M[500] 500 501 100 inc R1, R0 101 store M[501], R1 102 R0R1100 load R0, M[500] 10 IR ALU +1 11

11. Instruction Cycles Processor Control unitDatapath ALU Registers PC Controller Memory I/O Control /Status 10... load R0, M[500] 500 501 100 inc R1, R0 101 store M[501], R1 102 R0R1 1110 PC= 100 FetchDecode Fetch ops Exec. Store results clk PC= 101 FetchDecode Fetch ops Exec. Store results clk PC= 102 store M[501], R1 Fetch Fetch ops Exec. 11 Store results clk Decode 102 IR

12. Architectural Considerations  Clock frequency  Inverse of clock period  Must be longer than longest register-to- register delay in entire processor  Memory access is often the longest  The path that takes the longest time is called critical path. Clock period must be longer than the critical path. Processor Control unitDatapath ALU Registers IRPC Controller Memory I/O Control /Status

13. Memory: Two Memory Architectures Processor Program memory Data memory Processor Memory (program and data) HarvardPrinceton  Registers serve as short time storage space, the memory serves as the long time storage space  Memory:  Data  Program  Princeton  Harvard

14. Cache Memory  Memory access may be slow  On-chip memory (faster)  Off-chip memory (slower)  Cache is small but fast memory close to processor  Holds copy of part of memory that is most likely to be needed often  Underlying principle: If processor access a specific part of the memory, chances are it will need to access that immediate neighborhood of memory block again sometime soon  Hits and misses Processor Memory Cache Fast/expensive technology, usually on the same chip Slower/cheaper technology, usually on a different chip

15. Pipelining: Increasing Instruction Throughput 12345678 12345678 12345678 12345678 Fetch-instr. Decode Fetch ops. Execute Store res. 12345678 12345678 12345678 12345678 12345678 Wash Dry Time Non-pipelinedPipelined Time Pipelined pipelined instruction execution non-pipelined dish cleaningpipelined dish cleaning Instruction 1

16. Today’s Summary  Basic processor architecture  Processor (CPU) Datapath –ALU –registers Control Ubit –Controller –PC –IR  Memory Harvard Princeton Rowan?  Pipelining