1. Chapter 8 I/O

2. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-2 I/O: Connecting to Outside World So far, we’ve learned how to: compute with values in registers load data from memory to registers store data from registers to memory But where does data in memory come from? And how does data get out of the system so that humans can use it?

3. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-3 I/O: Connecting to the Outside World Types of I/O devices characterized by: behavior: input, output, storage  input: keyboard, motion detector, network interface  output: monitor, printer, network interface  storage: disk, CD-ROM data rate: how fast can data be transferred?  keyboard: 100 bytes/sec  disk: 30 MB/s  network: 1 Mb/s - 1 Gb/s These are BURST data rates:  frequency of bursts varies very widely  traffic is unpredictable: especially for servers on a network

4. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-4 I/O Controller Control/Status Registers (Register=group of latches) CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register Data Registers CPU transfers data to/from device Device electronics performs actual operation  pixels to screen, bits to/from disk, characters from keyboard Graphics Controller Control/Status Output Data Electronics CPU display

5. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-5 Programming Interface How are device registers identified? Memory-mapped vs. special instructions How is timing of transfer managed? Asynchronous vs. synchronous Who controls transfer? CPU (polling) vs. device (interrupts)

6. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-6 Memory-Mapped vs. I/O Instructions Instructions designate opcode(s) for I/O register and operation encoded in instruction Memory-mapped assign a memory address to each device register use data movement instructions (LD/ST) for control and data transfer in Pentia, I/O instr. use the SAME memory access except for 1 bit in Pentia, I/O instr. use the SAME memory access except for 1 bit! The “Glue” chips on system boards decide whether to direct a memory access to RAM or to a bus of I/O devices.

7. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-7 Transfer Timing I/O events generally happen much slower than CPU cycles. Synchronous data supplied at a fixed, predictable rate CPU reads/writes every X cycles Asynchronous data rate less predictable CPU must synchronize with device, so that it doesn’t miss data or write too quickly Not even Bill Gates can read data before it is available.

8. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-8 Transfer Control Who determines when the next data transfer occurs? Polling CPU keeps checking status register until new data arrives OR device ready for next data “Are we there yet? Are we there yet? Are we there yet?” Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. “Wake me when we get there.”

9. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-9 LC-3 Memory-mapped I/O (Table A.3) Asynchronous devices synchronized through status registers Polling and Interrupts the details of interrupts will be discussed in Chapter 10 Bit [15] is one when device ready to display another char on screen. Display Status Register (DSR) xFE04 Character written to bits [7:0] will be displayed on screen. Display Data Register (DDR) xFE06 Bits [7:0] contain the last character typed on keyboard. Keyboard Data Reg (KBDR) xFE02 Bit [15] is one when keyboard has received a new character. Keyboard Status Reg (KBSR) xFE00 FunctionI/O RegisterLocation

10. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-10 Input from Keyboard When a character is typed: its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) the “ready bit” (KBSR[15]) is set to one keyboard is disabled -- any typed characters will be ignored When KBDR is read: KBSR[15] is set to zero keyboard is enabled KBSR KBDR 15870 140 keyboard data ready bit An I/O device “Knows” when its Data register has been read. The device HW sets the STATUS BIT to 0.

11. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-11 Basic Input Routine new char? read character YES NO Polling POLL LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr... KBSRPtr.FILL xFE00 KBDRPtr.FILL xFE02

12. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-12 Simple Implementation: Memory-Mapped Input Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR.

13. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-13 Output to Monitor When Monitor is ready to display another character: the “ready bit” (DSR[15]) is set to one When data is written to Display Data Register: DSR[15] is set to zero character in DDR[7:0] is displayed any other character data written to DDR is ignored (while DSR[15] is zero) DSR DDR 15870 140 output data ready bit

14. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-14 Basic Output Routine screen ready? write character YES NO Polling POLLLDI R1, DSRPtr BRzp POLL STI R0, DDRPtr... DSRPtr.FILL xFE04 DDRPtr.FILL xFE06

15. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-15 Simple Implementation: Memory-Mapped Output Sets LD.DDR or selects DSR as input.

16. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-16 Keyboard Echo Routine Usually, input character is also printed to screen. User gets feedback on character typed and knows its ok to type the next character. new char? read character YES NO screen ready? write character YES NO POLL1LDI R0, KBSRPtr BRzp POLL1 LDI R0, KBDRPtr POLL2LDI R1, DSRPtr BRzp POLL2 STI R0, DDRPtr... KBSRPtr.FILL xFE00 KBDRPtr.FILL xFE02 DSRPtr.FILL xFE04 DDRPtr.FILL xFE06

17. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-17 I/O Trap Routines From LC3 OS..FILL BAD_TRAP ; x1E (expected address) ;This makes M[x001E] contain the value that ;the assembler eventually assigns to BAD_TRAP.FILL BAD_TRAP ; x1F.FILL TRAP_GETC ; x20.FILL TRAP_OUT ; x21... OS_KBSR.FILL xFE00 ; 1 memory word is initialized with xFE00 OS_KBDR.FILL xFE02 TRAP_GETC ; the address of this function ; is SYMBOLIZED by symbol TRAP_GETC LDI R0,OS_KBSR; wait for a keystroke BRzp TRAP_GETC ; a 2-instruction Loop. LDI R0,OS_KBDR ; read the keystroke into R0 RET ; and return (JMP R7,#0)

18. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-18 Interrupt-Driven I/O External device can: (1)Force currently executing program to stop; (2)Have the processor satisfy the device’s needs; and (3)Resume the stopped program as if nothing happened. Why? Polling consumes a lot of cycles, especially for rare events – these cycles can be used for more computation. Example: Process previous input while collecting current input. (See Example 8.1 in text.)

19. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-19 We will skip LC-3 Interrupt Details They are not very realistic. LC-3 has no memory protection features and the trap instruction does not put the CPU in supervisor mode.

20. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-20 Interrupt-Driven I/O To implement an interrupt mechanism, we need: A way for the I/O device to signal the CPU that an interesting event has occurred. A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal Software sets "interrupt enable" bit in device register. When ready bit is set and IE bit is set, interrupt is signaled. KBSR 1514 0 ready bit 13 interrupt enable bit interrupt signal to processor

21. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-21 Review Questions What is the danger of not testing the KBSR (Status Reg.) before reading data from the keyboard via KBDR? Do you think polling is a good approach for other devices, such as a disk or a network interface? (Are you unsure?) What is the advantage of using LDI/STI for accessing device registers? (Reminder: I in LDI means Indirect. The target address is IN the 16-bit word addressed by PCoffset9.)

22. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-22 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7) Example:  Payroll program runs at PL0.  Nuclear power correction program runs at PL6. It’s OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate.

23. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-23 Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases. If not set, continues with next instruction. If set, transfers control to interrupt service routine. EA OP EX S S F F D D interrupt signal? Transfer to ISR Transfer to ISR NO YES More details in Chapter 10.

24. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-24 Full Implementation of LC-3 Memory-Mapped I/O Because of interrupt enable bits, status registers (KBSR/DSR) must be written, as well as read.

25. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-25 Review Questions What is the danger of not testing the DSR before writing data to the screen? What is the danger of not testing the KBSR before reading data from the keyboard? What if the Monitor were a synchronous device, e.g., we know that it will be ready 1 microsecond after character is written. Can we avoid polling? How? What are advantages and disadvantages?

26. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-26 Review Questions Do you think polling is a good approach for other devices, such as a disk or a network interface? What is the advantage of using LDI/STI for accessing device registers?