1. Digital Circuit Review: Combinational Logic Logic operation –Need to know following two input gates: NAND, AND, OR, NOT, XOR –Need to know DeMorgan’s Theorems Real problem to truth table Karnaugh Map: –Box “1” or box “0” Largest supercell possible 2 n ones or zeros in each supercell Edges of Karnaugh map are connected Finish all ones or zeros Doesn’t matter (“d” or “x”) can be considered as either “1” or “0”.

2. Digital Circuit Review: Sequential Logic Flip Flips Timing diagram 1.When CLK signal arrives (rising edge or falling edge), FF will have outputs (Q and Q’) depending on the input (ex. D, or J, K). At this stage, ignore combinational logic if there exist in the circuit. 2.After finishing the output (Q and Q’), then work on the combinational logic, which typically determines the inputs (ex. D, or J, K) which will determine the output (Q and Q’) at next CLK signal Sequential circuit design: State Map 1.Construct a state map. 2.Convert the state map to truth map. Note: have to include all combination. Ex. If there are three outputs, Q 0, Q 1, and Q 2, then there are 8 states (combinations) that have to be listed. Some of them may be listed as “d”. 3.Prepare the inputs such that the outputs (Q 0, Q 1, and Q 2 ) at next state will follow the state map. 4.Convert the truth map to Karnaugh map: the inputs of FF (ex, D, or J, K) is the results in Karnuagh map, i.e. the value of the inputs of FF goes into cells. The outputs of FF is the inputs in the Karnaugh map.

3. Example 1 Ch. 13.20, three votes, two yes, pass, green light on, otherwise, fail, red light on. ABCF 0000 0010 0100 0111 1000 1011 1101 1111 C01 AB 0000 0101 1111 1001 F=AB+BC+AC 5V

4. Example 2: timing diagram Construct the timing diagrams below to ascertain the state diagram for both E=1 and E=0. Complete the state diagram to show the behavior of this 2-bit counter for E enabled. Complete the state diagram to show the behavior of this 2-bit counter for E disabled. 00 1001 ABCXNOR 0001 0010 0111 0100 1101 1000 1011 1110 11 01 10

5. Example 3: Sequential logic design Q2Q2 Q1Q1 D2D2 D1D1 0100 0010 1001 1101 Using D-type flip-flops and a single two-input logic gate, design a 2-bit state counter that will execute the sequence in this state diagram: Show the type of gate and the connections to the flip-flops needed for this counter on the schematic below: Karnaugh Map for D 2 Q1Q1 01 Q2Q2 010 100 D 2 =Q 1 ’Q 2 ’