1. Customized instruction-sets for embedded processors Fisher, J.A. Design Automation Conference, 1999. Proceedings. 36th, 1999, Page(s): 253 -257 speaker: Peter 12/04/2000

2. What’s the problem? It’s argued in this paper that architectural variety will soon again become an important topic. There are five major barriers to visible variety. Most of this paper is a discussion of these barriers and some solutions.

3. Introduction The major motivation for breaking the ISA is that doing so can sometimes lead to performance or performance/ price gains. “Processor performance was a key limitation in.” The prices and performance of Pentium Ⅱ ’s on the open market.

4. Pentium Ⅱ price and performance

5. The five major barriers Barrier1: The existing binaries problem Barrier2: The software toolchain Barrier3: Can low volume customized processors be competitive? Barrier4: Hardware development costs Barrier5: The product development cycle and customization

6. Barrier 1: binaries problem Most companies made “significant dents” in the market in mainstream. Performance drives “ISA drift”. The techniques making “ISA drift” acceptable on a large scale: object code translation, code caching, dynamic compiling, dynamic optimization,…etc.

7. Barrier2: software toolchain A new ISA implies a new toolchain. To automate all aspects of the variation of ISAs. – All toolchain changes support architectures in range. – Testing methodology uses architectures. – Preserve C semantics as best as you can – Fast and accurate simulation of everything.

8. Barrier3: low volume product A simple customized processor vs. A complex, large mass-market, high performance processor. System-On-Chip might change the equation. When every chip is made for the anticipated use only, the customized processors are more price competitive.

9. Barrier4: the hardware design cost In HP Lab., they do not spend a lot of time on it. There are some things to mention in this context: – Not having to pay much attention to binary compatibility allows simpler and more flexible design. – Software should always hopefully at min. cost – reconfigurable hardware

10. Barrier5: product development cycle Processor choices are usually bound 0.5 to 1.5 years ahead of first shipment. Tailor to an application area, not an application. Core capabilities that the application is likely to take advantage of, and key customizations can be used to good effect.

11. Conclusion The author outline the factor that he believe will cause instruction-set architecture to become performance driven families. The most important enablers will be the “mass-customization” of software toolchains.