1. Digital Baseband Converter Ying Xiang Xiuzhong Zhang Shanghai Astronomical Observatory China

2. Background  Analog BBC （ Base Band Converter ） 1. In VLBI data acquisition terminal, receiver bands are sent through the IF distributors to the base band converter. 2. Base band converters down-convert a portion of the receiver band using the so called SSB phasing method. Analog BBC is complex and expensive.  Adopting new digital technology to realize digital BBC (DBBC) may simplify the VLBI data acquisition terminal -Newest Technology for chip manufacture -Algorithm make DBBC approach the needed performance.

3. Why a Digital Base band Converter?  High cost to maintain a high efficiency of band use and very sharp rejection slopes using a switchable bank of analog filters.  The use of high-performance filters leads to potential difficulties when temperature and other variations cause the filter properties from antenna to antenna to be mismatched.  New disk based recorder is successful in SHAO, bbcs is the next item needing renewal preparing for e-vlbi.

4.  Bandwidth selection is highly desirable.  Higher overall reliability of the system because of the reduction in components and connections.  Lower cost and enhanced band efficiency due to sharper filter shapes are all to be expected with the use of digital filters.  Much better band pass matching between the different antennas in the array. Advantage of a Digital Base Band Converter

5. The digital filter for the VLBI was first developed in KSP, which was developed at the CRL (Communications Research Laboratory), Japan, and begun in 1994. There’re two kinds of implementations:

6. LO …… D D D S(t)IF A/D Subband 0 Subband 1 Subband N-1  Band pass filters with different center frequency choose different spectral band.

7.  Low pass filters and Local oscillator with different tunable frequency choose different spectral band.  Digital BBC is realized by the second implementation. LO S(t)IFA/D Subband 0 Subband 1 Subband N-1 LO N-1 LO 0 LO 1 …

8. Research on DBBC Abroad 1 、 Radioastronomy Institute, Italian National Research Coucil  Paper (written by Gino Tuccari) (1) Development of a Digital Base Band Converter : Basic Elements and Preliminary Results, Proceeding of IVS Symposium – New Technologies in VLBI, Korea, 2002.

9. Three parts: 1.5GHz sampler Max108 commercial board Xilinx VirtexE commercial board Altera NIOS commercial board for system control

10. 2 、 ALMA’s digital BBC (Gianni Comoretto) Theoretical analysis and simulation for DBBC  Papers (written by G. Comoretto) (1) ALMA memo #305 – A Digital BBC for the ALMA Interferometer (2) Design of a FIR filter using a FPGA, http://www.arcetri.astro.it/science/Radio/alma/Report _5a_2002.pdf

11. 3 、 Feb. 2002, NRAO (Ray Escoffier etc) gave digital filter card test report which used FPGAs (Field Programmable Gate Array Circuits) -- PrototypePrototype -- Test reportTest report -- Filter card test signal path Random data generator NCO #1 NCO #2 SUM RAM BUFFER Filter Card Under Test RAM BUFFER CORR 125MHz4GHz FIR output 62.5MHz

12. Layout of DBBC In I Q delay 90 o +: LSB -: USB DDS Digital filter sin cos DDC A/D Note: Digital filters ： spectral band selection and decimation. 90 o phase-shift network ： Hilbert transformation. DDS: Direct Digital Frequency Synthesizer

13. A/D Sampler  Commercial A/D sampler : Max105 -- maximum sampling: 800Msps -- 800mv full scale of input -- LVDS output -- 6 bits

14. DDS Implementation 12bit Phase increase Δθ Phase Accumulation clock NCO Output NCO Output sin cos Phase truncation LUT sin/cos

15. Digital filters Digital filters ： spectral band selection and decimation. Implementation: Finite impulse response (FIR). Polyphase filter CIC filter Compensation filter Decimation Rate ： 4~16383 Low pass Filtering Decimation Rate ： 2 ~ 8 -3dB Point Band Efficiency ： 90% Pass band Ripple ： <0.5dB Rejection band Attenuation ： >40dB

16. 1/8 Band Polyphase Filter  Specification: The number of taps: 152 Linear phase -3dB Point Band Efficiency ： 90% Pass band Ripple ： <0.5dB Rejection band Attenuation ： >40dB

17. 90º Phase Shift Network delay Hilbert I Q +:LSB -:USB  An ideal Hilbert transform provides a phase shift of 90 degrees for positive frequencies and –90 degrees for negative frequencies.  A delay match

18.  Specification of Hilbert filter ： 1. Bit length of coefficient: 9 2. -3dB point band efficiency: 98.4% 3. Number of Taps : 99 Characteristic in Spectral Domain of Hilbert Filter Figure illustration: Upper : impulse response Middle : amplitude Low : phase

19. Experimental Hardware Platform  The main task is to design different types of digital filters in FPGAs.  PCI DMA card : ADLINK 7300-B Local Micro- controller A/D Sampler Xilinx Virtex-II In Out PCI DMA Card Computer

20. Why Using FPGAs to Implement DBBC? Why Using FPGAs to Implement DBBC? The algorithms to realize digital filter require multiplication and addition in real-time, the unit is called MAC (Multiplication and Accumulation). Three choices of technology exist: 1. ASICs (Application Specific Integrated Circuits) 2. Programmable DSP (Digital Signal Processor) chips 3. FPGAs (Field Programmable Gate Array Circuits)

21.  ASICs can have multiple dedicated MACs that perform DSP functions in parallel. But they have high cost for low volume production and the inability to make design modifications after production makes them less attractive.

22.  Programmable DSP chips typically have only one MAC unit that can perform one MAC in less than a clock cycle. DSP processors are flexible, but they might not be fast enough. The reason is that the DSP processor is general purpose and has architecture that constantly requires instructions to be fetched, decoded and executed.

23.  The FPGA architecture allows multiple MACs and pipelining. Their ability to be modified easily makes them an ideal candidate for DSP functions. The only drawback is the speed, and this can easily be overriden by using computational algorithms suitable for FPGAs.

24. Function Industry ’ s Fastest DSP Processor COre Xilinx Virtex-E- 08 Xilinx Virtex-II pro MACs per second - Multiply and accumulate -8×8 bit 8.8 Billion 128 Billion 1 Trillion FIR Filter -256-tap,linear phase -16-bit data/coefficients 17MSPS @1.1GHz 160MSP S @160M Hz 300MSPS @300MH z FFT -1024 point ， complex data -16-bit real & imag 7.7μs @800MHz 41μs @100M Hz 1μs @150MH z Performance Comparison between DSP Processor and Xilinx FPGA

25.  PCI DMA interface card -- ADLINK 7300-B  Max105 A/D sampler -- 6 bits -- 800mv full scale  Xilinx Virtex-II -- XC2v1000 -- 100MHz Clock  LVDS interface between Virtex-II and A/D sampler  Winbond 77E58 for system control DBBC Hardware Platform in SHAO

26. Simulation results  Simulation in Modelsim and Matlab: 1.The requirement in this design is to get low side band. 2.Simulation_1 shows the result when input is upper side band. Simulation_2 shows the result when input is low side band. --Simulation_1Simulation_1 --Simulation_2Simulation_2 3. Simulation conclusion

27. Thanks !