1. HIFI Mixer CDR Band 3 and 4 Mixer Units SIS Device Fabrication
DIMES, TU Delft
T. Zijlstra, M. Kroug, M. Zuidam,
N. Iosad, B. de Lange, J.R. Gao, T.M. Klapwijk
SRON
B. Jackson, G. de Lange

2. Contents historical overview device production and testing
Band 3 device geometry, production, and testing
Band 4 device geometry and production
problems and solutions
DC test results
programmatics
ongoing technology developments
AlNx barriers, CMP, e-beam lithography

3. Historical Overview 1 pre-1997 (RUG) 1997-1999 1999-2000 (DIMES)
Nb SIS
Nb SIS + Al/SiO2/Al tuning circuits (Kovtonyuk, Jegers)
NbTiN deposition process (Iosad)
Nb SIS for JCMT (Jackson)
Nb SIS + NbTiN/SiO2/NbTiN
Nb SIS + NbTiN/SiO2/Al circuits
(DIMES)
transfer of SIS process to Delft (Zuiddam, Iosad)

4. Historical Overview 2 2000-2001 2001-2002
re-establishment of Nb SIS process (Zijlstra, Zuiddam)
delivery of devices to JCMT and ALMA
AlNx tunnel barrier development (Iosad)
re-establishment of Nb SIS + NbTiN/SiO2/Al (Zijlstra, Zuiddam)
delivery of SIS 19 batches (19-03, 19-06, 19-08, 19-10)
19-03, 19-06: contact resistance, junction heating
19-08: band 3 design verification, DM mixer
first batches with NbTiN ground planes from JPL (Zijlstra, Kroug)
turnover of personnel
addition of Kroug, Zijlstra on leave for 6 months (returned 8/02)

5. Band 3 FM Design device geometry SIS 20 mask-set
NbTiN ground plane: Tc,NbTiN ~ 14.4 K, ρn,NbTiN ~ 110 µΩ·cm
Nb/Al-AlOx/Nb SIS: Jc = 8-15 kA/cm2, A ~ 1 µm2
sputtered SiO2 dielectric
Al wiring layer: ρ4K ~ 0.4 µΩ·cm
SIS 20 mask-set
6 sectors of 81 devices for Band 3 (+ 2 sectors for KOSMA)
2 designs x 3 sectors each
suspended and unsuspended RF designs
4 junction areas x 4 transformer sizes (production/design tolerances)
5 devices per scaling per sector
1 complete wafer could be enough for FM

6. Band 3 Production Flow 1 substrate cleaning
ground plane deposition and patterning
image-reversal resist pattern definition (AZ 5214E)
room-temperature DC sputter-deposition of 320-nm NbTiN
liftoff and substrate cleaning
trilayer deposition
DC sputter-deposition of 100-nm Nb + 6-nm Al
oxidation of Al in load-lock
DC sputter-deposition of 100-nm Nb

7. Band 3 Production Flow 2 junction pattern definition junction etch
UV400 positive resist definition (AZ 5214E)
junction etch
1st RIE: RIE of Nb in SF6 + O2
2nd RIE: resist recessing by O2 RIE (reduce size by nm)
Nordiko: RF sputter etch of Al in Ar

8. Band 3 Production Flow 3 junction passivation junction lift-off
anodic oxidation of junction side-walls
RF sputter deposition of 250-nm SiO2
junction lift-off
physical brushing
chemical cleaning
RF sputter etch

9. Band 3 Production Flow 4 wiring deposition and patterning (etch)
DC sputter deposition of 400-nm Al
positive resist pattern definition (HPR)
RIE of Al in BCl3 + N2 + Cl2
substrate cleaning
wiring deposition and patterning (lift-off)
image-reversal resist pattern definition
DC sputter-deposition of 400-nm Al
lift-off and substrate cleaning

10. Band 3 Production Flow 5
passivation layer and contact pad deposition and patterning
option 1
DC sputter-deposition of 75-nm Nb + 50-nm Au
define positive image of contact pads in resist
wet etch of Au
RIE of Nb in SF6+O2
RF sputter-deposition of 150-nm of SiO2
lift-off SiO2 and clean substrate
option 2
deposit SiO2 layer
define negative image of contact pads in resist (image-reversal)
RIE of SiO2 in CHF3 + O2
deposit Nb/Au bilayer
lift-off Nb/Au and clean substrate

11. Band 3 Testing Flow substrate diced into 8 sectors
mounting of samples onto dip-stick carriers
spring-contact to 16 test pads
dip-stick testing of sectors at DIMES
7 test structures per sector (4-point measurements)
24 um2, 9 um2, four 1- or 2x1-µm2, 1 long NbTiN or Al wire
I-V curves at 4.2 K
R-T curves from 1 or 2 sectors (Tc + ρn of NbTiN, Tc of Nb)
promising sectors packaged and shipped to SRON
dicing/polishing of individual devices occurs at SRON
all wafer- or device-level environmental testing occurs at SRON

12. Band 4 FM Design device geometry SIS 21 mask-set
NbTiN ground plane (JPL): Tc,NbTiN ~ 16 K, ρn,NbTiN ~ 60 µΩ·cm
Nb/Al-AlOx/Nb SIS: Jc ~ 8-15 kA/cm2, A ~ 1 µm2
sputtered SiO2 dielectric
Al wiring layer: ρ4K ~ 0.4 µΩ·cm
SIS 21 mask-set
6 sectors of 81 Band 4 devices (+ 2 sectors for Band 3)
3 basic designs x 2 sectors each
uncertainties in NbTiN parameters
4 junction areas x 6 transformer sizes (production/design tolerances)
3-4 devices per scaling per sector
2 wafers likely needed for FM

13. Band 4 Production and Testing Flow
substrate cleaning and shipment to JPL
~ 4 wafers per shipment (2 films in stock, > 4 expected in October)
ground plane deposition at JPL
elevated-temp. deposition of AlN buffer nm NbTiN (J. Stern)
wafers returned to DIMES via SRON
ground plane patterning
substrate cleaning
positive resist pattern definition
RIE of NbTiN in SF6 + O2
remainder of process identical to Band 3

14. Problems and Solutions
technical
contact resistance and junction heating
wiring-to-junction contact: extra sputter-etch after SiO2 lift-off
end-point control of Ar sputter-etch of Al
extra process calibration and/or test wafers needed
potential damage to edge of barrier during Ar sputter etch
resist recessing to make top electrode smaller than bottom
failure of first runs w. JPL ground planes
cause unknown, step-coverage over etched ground plane is okay
programmatic
re-establishment of process at DIMES (completed in fall of 2001)
temporary loss of personnel in early-mid 2002
Zijlstra (6 month leave-of-absence), Kroug (learning period)
returned to “full-strength” in August, focus 100 % on HIFI until Nov./Dec.

15. I-V Curves, 1 µm2 junctions
Status, DC Test Results
I-V Curves, 1 µm2 junctions
typical SIS 19/20 batch (1 μm2)
RnA Ω·μm2
Rj/Rn 10-35
Vgap mV
dVg mV
Rseries 0-10 Ω
SIS results (1 μm2)
RnA 30 Ω·μm2
Rj/Rn 15-35
Vgap mV
Rseries Ω
Yield 76 %
19-08
20-02

16. Projected Schedule Sept. – Dec., 2002 Dec. 2002 – Mar. 2003
focus on HIFI (Kroug + Zijlstra full-time until Dec.)
band 3 FM
masks ready in Aug., production started in Sept., first batch delivered Oct. 3
upcoming deliveries: at least 2 follow-up batches in Oct.-Dec.
band 4 DM (and possibly FM)
design ready in Sept., masks ready in Oct., production started
deliveries: at least 2 batches in Oct.-Dec.
Dec – Mar. 2003
redesign of band 4 mask at SRON (if needed)
band 4 FM production (if needed)
Jan. – Oct. 2003
band 3 and 4 FS production (+ process upgrade, if needed)

17. Resources and Commitments
available resources
device production and technology development (DIMES)
1.5 production engineers (permanent staff) + 1 post-doc (3-year contract)
post-fabrication dicing and testing (TU Delft)
0.5 persons
documentation and quality assurance support
0.25 persons + support from SRON
other commitments
production for JCMT (MRAO, 350 GHz array receiver)
project nearing completion
development and production for ALMA (band 9 = GHz)
reduced effort until Dec. ‘02

18. Parallel Development, AlNx
motivation
enable good-quality, high-Jc junctions (Bumble et. al)
improved RF band-width
improved RF coupling
status
trilayer recipe developed (Iosad)
integration w. Nb SIS started (Kroug)
2 batches completed
1 combined with EBL
to be done
characterize process variability
run-to-run, device-to-device
process stabilization
integration w. NbTiN process
Junction Quality vs. RnA
(SNAP process)

19. Parallel Development, EBL
motivation
improved device yield for sub-µm junctions
potential to shorten design cycle
status
feasibility of double-layer resist (SNR/AZ) has been demonstrated
alignment accuracy tested
integration with Nb SIS process started (Kroug)
2 batches completed, 1 combined with AlNx barrier
to be done
determine impact on device yield for Nb SIS process
device-to-device and run-to-run statistics
integrate with NbTiN process and determine impact on device yield

20. Parallel Development, CMP
motivation
improved device yield for sub-µm junctions
improved electrical/thermal contact to junctions (experience from KOSMA)
status
machine installed
characterization started (blanket films and structured wafers)
to be done
process characterization/optimization
integration with SIS process (esp. with EBL)
development on hold (no manpower allocated)