Presentation is loading. Please wait.

Presentation is loading. Please wait.

The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What."— Presentation transcript:

1 The Spartan 3e FPGA

2 CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What do all these things mean? LUT, Slice, BRAM, DCM, IOB, CLB...  Two important documents (linked to the class web site) Spartan3e Family Complete Data Sheet Spartan3e User Guide

3 CS/EE 3710 What’s on the chip?

4 CS/EE 3710 What’s on the chip? CLB (Configurable Logic Blocks) Logic and flip flops 1,164 CLBs on our chip Each CLB is 4 Slices 500k total “system gates”

5 CS/EE 3710 What’s on the chip? IOB (Input Output Blocks) Communicate off chip Our chip has 232 total pins in a 320 BGA package

6 CS/EE 3710 What’s on the chip? BRAM (Block RAM) On-chip SRAM 18k bits per block 20 blocks on our chip

7 CS/EE 3710 What’s on the chip? Multiplier Custom 18x18 multiplier One per RAM block...

8 CS/EE 3710 What’s on the chip? DCM (Digital Clock Manager) Clock generation and distribution Four on our chip

9 CS/EE 3710 What’s on the chip? Programmable Interconnect Connect everything together Perhaps the most critical part of the chip!

10 CS/EE 3710 CLB: Configurable Logic Block  4 “Slices” per CLB The slices work together to make logic, flip flops, distributed RAM, or shift registers Connected to other CLBs through Switch Matrix

11 CS/EE 3710 Left and Right Slices  SRL16 = 16-bit shift register  RAM16 = 16-bit RAM (16x1 bit memory)  LUT4 = four-bit lookup table (16x1 bit memory)  SLICEM = slice that can be memory or logic  SLICEL = slice that can only be logic

12 CS/EE 3710 What’s Really in a Slice?

13 CS/EE 3710 LUT 4 – Basic Building Block

14 CS/EE 3710 LUT 4 – Basic Building Block

15 CS/EE 3710 Slice Muxes extend LUT4

16 CS/EE 3710 One CLB – up to LUT7

17 CS/EE 3710 Top Half of a SliceM (left)

18 CS/EE 3710 Top Half of a SliceM (left)

19 CS/EE 3710 Logic-only (combinational)

20 CS/EE 3710 Logic + register (sequential)

21 CS/EE 3710 Just register

22 CS/EE 3710 Fast Carry Path (arithmetic)

23 CS/EE 3710 Fast Carry Path (arithmetic)

24 CS/EE 3710 Fast Carry Path (arithmetic)

25 CS/EE 3710 Mapping to CLBs  Each LUT can go through a flip flop So, these circuits map to the same number of Slices

26 CS/EE 3710 Mapping to CLBs  How about these?

27 CS/EE 3710 Mapping to CLBs  How about these?

28 CS/EE 3710 CLB Summary  Each CLB = 4 slices  Each slice contains 2 LUT-4 LUT can be random logic, or 16x1bit RAM or SR 2 flip flop MUXs Carry logic  ISE reports how many slices you use among lots of other things...

29 CS/EE 3710 IO Blocks  Connections to the outside world Each pin can be configured a large number of ways Different signaling voltages and drive currents

30 CS/EE 3710 IO Blocks  Connections to the outside world Each pin can be configured a large number of ways Different signaling voltages and drive currents NOTE! No 5v!

31 CS/EE 3710 Inside an IOB

32 CS/EE 3710 Interconnect  Actually the most important part of the FPGA! Consumes the most area on the die Consumes the most power on the die In most cases, wires limit the performance  But, hardly mentioned in the datasheet People are more impressed with logic

33 CS/EE 3710 Interconnect  RAM-programmable switches 2,270,208 bits of configuration RAM! Compare to 368,640 total bits of Block RAM or 74,752 total bits of Distributed RAM (LUTs)  Hierarchical organization Many fast, short wires with small drive Fewer longer wires with high drive LOTS of work goes into picking just the right mix!

34 CS/EE 3710 Interconnect

35 CS/EE 3710 Interconnect Four types of wires

36 CS/EE 3710 Clock Routing  Routed on a separate dedicated network Another reason to avoid gated clocks  Recursive “Fish bone” network that minimizes clock skew  Clocks come from off-chip, or from a DCM (dig. Clk man)

37 CS/EE 3710 Spartan XC3E500S

38 CS/EE 3710 Block RAM We’ve seen details of these already…

39 CS/EE 3710 Behavioral Template Dual-port 1 R/W 1 R

40 CS/EE 3710 Structural Template

41 CS/EE 3710 Structural Template

42 CS/EE 3710 Distributed RAM

43 CS/EE 3710 Distributed RAM

44 CS/EE 3710 Distributed RAM Dual-Port Distributed RAM

45 CS/EE 3710 Distributed RAM Dual-Port Distributed RAM

46 CS/EE 3710 Digital Clock Manager (DCM)

47 CS/EE 3710 Digital Clock Manager (DCM)

48 CS/EE 3710 Digital Clock Manager (DCM)

49 CS/EE 3710 Clock Skew

50 CS/EE 3710 Clock Skew

51 CS/EE 3710 Multipliers

52 CS/EE 3710 Multipliers

53 CS/EE 3710 Synthesis Output (mips example)

54 CS/EE 3710 Synthesis Output (mips example)

55 CS/EE 3710 Synthesis Output (mips example)

56 CS/EE 3710 Synthesis Output (mips example)

57 CS/EE 3710 Synthesis Output (mips example)

58 CS/EE 3710 Implement Output (mips example)

59 CS/EE 3710 Implement Output (mips example)

60 CS/EE 3710 Implement Output (mips example)

61 CS/EE 3710 Implement Output (mips example)

62 CS/EE 3710 Implement Output (mips example)

63 CS/EE 3710 Implement Output (mips example)

64 CS/EE 3710 Implement Output (mips example)

65 CS/EE 3710 Conclusion  FPGAs are complex beasts! Made to be very general and flexible  ASIC vs. FPGA? Rule of thumb, FPGA about 5 times slower clock than ASIC FPGAs consume more power FPGAs are bigger for the same function ASICs are much more expensive to develop NRE – Non-Recurring Engineering

66 CS/EE 3710 ASIC vs. FPGA

Download ppt "The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What."

Similar presentations

Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.

Lecture 11-1 FPGA We have finished combinational circuits, and learned registers. Now are ready to see the inside of an FPGA.
ECE 506 Reconfigurable Computing ece. arizona

ECE 506 Reconfigurable Computing ece. arizona
Lecture 15 Finite State Machine Implementation

Lecture 15 Finite State Machine Implementation
Digital Design Copyright © 2006 Frank Vahid 1 FPGA Internals: Lookup Tables (LUTs) Basic idea: Memory can implement combinational logic –e.g., 2-address.

Digital Design Copyright © 2006 Frank Vahid 1 FPGA Internals: Lookup Tables (LUTs) Basic idea: Memory can implement combinational logic –e.g., 2-address.
EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 5 Programmable.

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 5 Programmable.
Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.
Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.

Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.
EECE579: Digital Design Flows

EECE579: Digital Design Flows
Implementing Logic Gates and Circuits Discussion D5.1.

Implementing Logic Gates and Circuits Discussion D5.1.
Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.
Evolution of implementation technologies

Evolution of implementation technologies
Programmable logic and FPGA

Programmable logic and FPGA
Introduction to Field Programmable Gate Arrays (FPGAs) COE 203 Digital Logic Laboratory Dr. Aiman El-Maleh College of Computer Sciences and Engineering.

Introduction to Field Programmable Gate Arrays (FPGAs) COE 203 Digital Logic Laboratory Dr. Aiman El-Maleh College of Computer Sciences and Engineering.
February 4, 2002 John Wawrzynek

February 4, 2002 John Wawrzynek
Lecture 3 1 ECE 412: Microcomputer Laboratory Lecture 3: Introduction to FPGAs.

Lecture 3 1 ECE 412: Microcomputer Laboratory Lecture 3: Introduction to FPGAs.
CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic: Internal Organization of an FPGA José Nelson Amaral.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic: Internal Organization of an FPGA José Nelson Amaral.
1 Introduction A digital circuit design is just an idea, perhaps drawn on paper We eventually need to implement the circuit on a physical device –How do.

1 Introduction A digital circuit design is just an idea, perhaps drawn on paper We eventually need to implement the circuit on a physical device –How do.
1. 2 FPGAs Historically, FPGA architectures and companies began around the same time as CPLDs FPGAs are closer to “programmable ASICs” -- large emphasis.

1. 2 FPGAs Historically, FPGA architectures and companies began around the same time as CPLDs FPGAs are closer to “programmable ASICs” -- large emphasis.
Introduction to FPGA’s FPGA (Field Programmable Gate Array) –ASIC chips provide the highest performance, but can only perform the function they were designed.

Introduction to FPGA’s FPGA (Field Programmable Gate Array) –ASIC chips provide the highest performance, but can only perform the function they were designed.

Similar presentations

Ads by Google