1. Students: Shai Amara Shuki Gulzari Project instructor: Ina Rivkin Matrix Multiplication on SOPC

2. Project Goals: Implementing Matrix multiplication of different sizes of matrixes in hardware on Sopc

3. Why to implement it on hardware? 1) Today the Processor has to run long loops and perform many transactions for simple matrix multiplication. 2) We can save precious Processor time and in simple few orders the Processor will execute hardware solution to save time. 3) The Processor will be able to choose the way to be informed about the completion of the operation - Interrupt or polling.

4. Requirements :  To multiply NxN Integer matrixes.  To inform the Processor about the completion of the multiplication by polling or interrupts.  The Processor will inform the multiplication unit using a configuration register (located in the unit) about the size of the matrixes, their location in memory (optional), the preferred way to be acknowledged about the completion of the operation (polling or interrupt). nxn

5. first optional implementation  The processor will initiate the transfer of the two matrixes into the inner memory of the multiplication unit.  The multiplication unit will perform the multiplication and store the result matrix also in its inner memory.  The multiplication unit will inform the processor about the completion of the operation according to the configuration register (interrupt/polling).  In this implementation our multiplication unit is located on the PLB.

6. Processor Matrix Multiplication PLB/OPB bridge Uart PLB OPB Block Diagram for first optional implementation

7. Second optional implementation  The processor will inform the multiplication unit about the location of the matrixes in memory using the configuration registers.  The multiplication unit will perform the multiplication using the DMA and will store the result matrix in its inner memory space.  The multiplication unit will inform the processor about the completion of the operation according to the configuration register (interrupt/polling).  In this implementation our multiplication unit is located on the OPB.

8. Processor Matrix Multiplication PLB/OPB bridge Uart PLB OPB MEMORY Block Diagram for second optional implementation DMA

9. Schedule During the next 3 weeks: Learning EDK Learning Vhdl During the next 3-6 weeks: Adding simple peripheral unit to the Sopc that performs simple logic operation that will work with the memory (B- block)