1. 11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical structure –CMOS –Dynamic circuits (Ring oscillators)

2. 11/5/2004EE 42 fall 2004 lecture 282 n P oxide insulator n drain - + source gate NMOS =device which carrier current using electrons but on the surface of a p-type substrate (p-type substrate means that no electrons are available) n P oxide insulator n drain source N-MOS In this device the gate controls electron flow from source to drain. (in the absence of gate voltage, current is blocked) gate V GS > V t If we increase gate voltage to a value greater than V t then a conducting channel forms between source and drain. (“Closed switch”)

3. 11/5/2004EE 42 fall 2004 lecture 283 CMOS = Complementary MOS (PMOS is a second Flavor) n P oxide insulator n drain source N-MOS In this device the gate controls electron flow from source to drain. The NEW FLAVOR! P-MOS It is made in p-type silicon. It is made in n-type silicon. (In n- type silicon no positive charges (“holes”) are normally around.) In this device the gate controls hole flow from source to drain. gate source drain n-type Si P-MOS gate pp

4. 11/5/2004EE 42 fall 2004 lecture 284 PMOS It is made in n-type silicon. In this device the gate controls hole flow from source to drain. source drain n-type Si p gate + - p What if we apply a big negative voltage on the gate? If |V GS |>|V t | (both negative) then we induce a + charge on the surface (holes) source drain n-type Si P-MOS gate pp |V GS |>|V t |

5. 11/5/2004EE 42 fall 2004 lecture 285 NMOS and PMOS Compared NMOS “Body” –p-type Source – n-type Drain – n-type V GS – positive V T – positive V DS – positive I D – positive (into drain) PMOS “Body” –n-type Source – p-type Drain – p-type V GS – negative V T – negative V DS – negative I D – negative (into drain) G n n IDID D S p B G p IDID D S n B IDID 4 3 2 1 V DS V GS =3V 1 mA V GS =0 (for I DS = 1mA) 4 3 2 1  V DS V GS =  3V 1 mA V GS =0 IDID (for I DS = -1mA)

6. 11/5/2004EE 42 fall 2004 lecture 286 NMOS circuit symbol CIRCUIT SYMBOLS G S D A small circle is drawn at the gate to remind us that the polarities are reversed for PMOS. PMOS circuit symbol G S D

7. 11/5/2004EE 42 fall 2004 lecture 287 PMOS Transistor Switch Model Operation compared to NMOS: It is complementary. For PMOS for the normal circuit connection is to connect S to VDD (The function of the device is a “pull up”) V G = V DD Switch is open : Drain (D) is disconnected from Source (S) when V G = V DD V G =0 Switch is closed: Drain (D) is connected to Source (S) when V G =0 G S D V DD Switch OPEN V DD G S D V=0 Switch CLOSED S D G

8. 11/5/2004EE 42 fall 2004 lecture 288 PMOS Model Refinement PMOS transistor has an equivalent resistance R DP when closed The circuit symbol G D S P Ch S D G R DP The Switch model CGSCGS There is also a gate capacitance C GS, just as in NMOS

9. 11/5/2004EE 42 fall 2004 lecture 289 CMOS Challenge: build both NMOS and PMOS on a single silicon chip NMOS needs a p-type substrate PMOS needs an n-type substrate Requires extra process steps oxide P-Si n-well p pnn G D G D S S

10. 11/5/2004EE 42 fall 2004 lecture 2810 THE BASIC STATIC CMOS INVERTER v out v in V DD PMOS NMOS For V in < 1V NMOS off, PMOS on For V in > 1.5V NMOS on, PMOS off source drain source drain Example for Discussion: NMOS: V Tn = 1 V PMOS: V Tp = -1 V Let V DD = 2.5V V out = 0 V out = V DD V in V out V DD V in V DD V out

11. 11/5/2004EE 42 fall 2004 lecture 2811 THE BASIC STATIC CMOS INVERTER Quasi-static operation (ignoring transients) v out v in V DD PMOS NMOS For V in < 0.5V NMOS off, PMOS on For V in > 2V NMOS on, PMOS off source drain source drain Example for Discussion: NMOS: V Tn = 0.5 V PMOS: V Tp = - 0.5 V Let V DD = 2.5V V out = 0 V out = V DD V in V out V DD V in V DD V out

12. 11/5/2004EE 42 fall 2004 lecture 2812 CMOS INVERTER TRANSFER CURVE v out v in V DD PMOS NMOS

13. 11/5/2004EE 42 fall 2004 lecture 2813 CHAIN OF CMOS INVERTERS V out If the input is toggled, the state of every inverter will change and there will be a gate delay for every gate caused by the combination of the output resistance of the switching devices combined with the input capacitance of the following stage. Let’s estimate the stage delay. STAGE M V DD V V V v in V DD V out V in V DD

14. 11/5/2004EE 42 fall 2004 lecture 2814 CHAIN OF CMOS INVERTERS STAGE-M When the input V M is high, the lower (NMOS) switch is closed and according to our model the resistor R N discharges the input capacitance of the next gate, the capacitors C GN and C GP in parallel. The time constant is R N ( C GN + C GP ) so the gate delay is 0.69 R N ( C GN + C GP ). We do not consider here the capacitance of the gates in Stage M, because they load Stage M-1, and contribute to its delay. V DD V M+1 VMVM DD V the model VMVM V DD V M+1 RNRN C GP C GN gate delay if input HIGH “Open” “Closed” MM+1 V DD

15. 11/5/2004EE 42 fall 2004 lecture 2815 Core Circuit for “Pull-Down” Transition Circuit only contains one resistor and two capacitors Capacitors C Gp and C Gn … how can they be combined into one? Capacitors share one node; the other nodes are held at constant voltages. v C (t) V = 0 1 V = V DD 2 C 2 C 1 i() 2 () i 1 t) t it ( KCL: currents sum at common node, ie node capacitance is SUM (parallel capacitor formula). “Virtually Parallel” Capacitors

16. 11/5/2004EE 42 fall 2004 lecture 2816 Pull-Down Equivalent Circuit Two capacitors add for finding the charging current  applies to gate capacitances R n v out1 D C Gn + C Gp t =0+ Precharge: V DD v out1 = v in2 v in1 + - V DD v out2 Lets once more associate circuit above to the actual inverter circuit.

17. 11/5/2004EE 42 fall 2004 lecture 2817 Equivalent circuit vs actual circuit R n v out1 D C Gn + C Gp t =0+ Precharge: V DD 1) Remove inactive device v out1 v in2 v in1 + - V DD v out2 3) Replace NMOS pull- down by by its output equivalent. 2) Replace load devices by their input equivalents

18. 11/5/2004EE 42 fall 2004 lecture 2818 Gate Delay from Pull-Down Equivalent Circuit Capacitor is precharged to V DD and discharged to ground through resistance R n. R n v out1 D C Gn + C Gp t =0+ Precharge: V DD If we define the switching delay as the time for the output voltage to swing halfway to its new steady-state value, we will find the switching delay is 0.69RC. [remember 0.5 = exp(-0.69)] t/RC V DD 0.69 2 V DD exp(-t/RC) V out1 We can compute the delay easily. It is just an RC delay.

19. 11/5/2004EE 42 fall 2004 lecture 2819 CHAIN OF CMOS INVERTERS STAGE-M When the input V M is low, the upper (PMOS) switch is closed and according to our model the resistor R P charges the input capacitance of the next gate, the capacitors C GN and C GP in parallel. The time constant is R P ( C GN + C GP ) so the gate delay is 0.69 R P ( C GN + C GP ). Normally we try to have equal rising and falling gate delay, so for the simple inverter we design the transistors so R P = R N. V DD V M+1 VMVM DD V gate delay if input LOW “CLOSED” “Open” MM+1 the model V DD V M+1 RPRP C GP C GN VMVM V DD

20. 11/5/2004EE 42 fall 2004 lecture 2820 CMOS PARAMETERS 3 generations of CMOS Return

21. 11/5/2004EE 42 fall 2004 lecture 2821 Interconnect layers On top of the transistor layers, many metal layers interconnect the logic Illustration Actual TEM photo

22. 11/5/2004EE 42 fall 2004 lecture 2822 CHAIN OF CMOS INVERTERS TO MEASURE  delay If the input is toggled, the state of every inverter will change and there will be a gate delay for every gate. Suppose there are 1001 gates and we move the input switch from V DD to ground. 1001 gate delays later the output will go from ground to V DD. V out STAGE 1 V DD STAGE 101 But suppose in the meantime we moved the switch to connect to V out (which is initially zero). At at time equal to exactly 1001 gate delays, the input to stage 1 will go high, and after another equal time it will go low, etc. We have created a “RING OSCILLATOR”, which toggles at a frequency equal to 1/(1001  delay ). Such ring oscillators are commonly used to estimate the performance of a technology. No switch is actually needed, the output is permanently wired to the input, and the oscillations start when power is applied.

23. 11/5/2004EE 42 fall 2004 lecture 2823 CMOS INVERTERS DRIVING ANY LOAD If we substitute the switch model for the transistors we have the following circuit: V DD No matter what the load is, the behavior is the same: the stage delay is 0.69RC where C= C LOAD and R= R N if input is switched high or R= R P if input is switched low. V out C LOAD R n D V DD R p V out The actual load consists of whatever gates are attached to the node plus any additional capacitance. In the next lecture we will compute the gate capacitance on the input to any NAND logic block for example. As another example, if an external wire is attached to a node with the wire going to a printed circuit board, we will have a load of several pF.