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ELEN 468 Lecture 241 ELEN 468 Advanced Logic Design Lecture 24 Design for Testability
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ELEN 468 Lecture 242 Test Cost Test pattern generation Fault simulation Generation of fault sites information Test equipment Test process Test cost may overweight design cost
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ELEN 468 Lecture 243 Why Design for Testability? Testability is a design characteristic that influences various costs associated with testing It allows for Device status to be determined Isolation of faults Reduce test time and cost
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ELEN 468 Lecture 244 Controllability Ability to establish a specific signal value at each node by setting circuit’s inputs Circuits typically difficult to control: decoders, circuits with feedback, oscillators, clock generators …
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ELEN 468 Lecture 245 Observability Ability to determine the signal value at any node in a circuit by controlling the circuit’s inputs and observing its output
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ELEN 468 Lecture 246 Predictability Ability to obtain known output values in response to given input stimuli Factors affecting predictability Initial state of circuit Races Hazards … …
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ELEN 468 Lecture 247 Difficult Test Cases Sequential logic is more difficult to test than combinational logic Control logic is more difficult to test than data-path logic Random logic is more difficult to test than structured bus-oriented designs Asynchronous design is more difficult to test than synchronous design
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ELEN 468 Lecture 248 Quantify Testability Need approximate measure of: Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by observing primary outputs Uses: Analysis of difficulty of testing internal circuit parts – redesign or add special test hardware Guidance for algorithms computing test patterns – avoid using hard-to-control lines Estimation of fault coverage Estimation of test vector length
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ELEN 468 Lecture 249 Types of Measures SCOAP – Sandia Controllability and Observability Analysis Program Combinational measures: CC0 – Difficulty of setting circuit line to logic 0 CC1 – Difficulty of setting circuit line to logic 1 CO – Difficulty of observing a circuit line Sequential measures – analogous: SC0 SC1 SO
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ELEN 468 Lecture 2410 Range of SCOAP Measures Controllabilities – 1 (easiest) to infinity (hardest) Observabilities – 0 (easiest) to infinity (hardest) Combinational measures: Roughly proportional to # circuit lines that must be set to control or observe given line Sequential measures: Roughly proportional to # times a flip-flop must be clocked to control or observe given line
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ELEN 468 Lecture 2411 Controllability Examples
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ELEN 468 Lecture 2412 Observability Examples
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ELEN 468 Lecture 2413 Goal of Design for Testability (DFT) Improve Controllability Observability Predictability
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ELEN 468 Lecture 2414 Design and Test Trade-off Most DFT ( Design for Testability ) techniques need extra hardware, or modification to circuits that may affect performances DFT need to consider the cost trade-off between design and test
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ELEN 468 Lecture 2415 DFT Methods DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan
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ELEN 468 Lecture 2416 Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: Avoid asynchronous (unclocked) feedback Make flip-flops initializable Avoid redundant gates Avoid large fanin gates Provide test control for difficult-to-control signals Avoid gated clocks Design reviews conducted by experts or design auditing tools Disadvantages of ad-hoc DFT methods: Experts and tools not always available Test generation is often manual with no guarantee of high fault coverage Design iterations may be necessary
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ELEN 468 Lecture 2417 Scan Design Circuit is designed using pre-specified design rules Test structure (hardware) is added to the verified design: Add a test control (TC) primary input Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode Make input/output of each scan shift register controllable/observable from PI/PO
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ELEN 468 Lecture 2418 Scan Design Rules Use only clocked D-type of flip-flops for all state variables At least one PI pin must be available for test; more pins, if available, can be used All clocks must be controlled from PIs
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ELEN 468 Lecture 2419 Correcting a Rule Violation All clocks must be controlled from PIs Comb. logic Comb. logic D1 D2 CK Q FF Comb. logic D1 D2 CK Q FF Comb. logic
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ELEN 468 Lecture 2420 Scan Storage Cell D Si N/T’ Clk Q, So SSC D Q
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ELEN 468 Lecture 2421 Scan Flip-Flop (SFF) D N/T’ Si Clk Q Q MUX D flip-flop Master latchSlave latch Logic overhead
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ELEN 468 Lecture 2422 Scan Methods C1C2 C1 MUX Si
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ELEN 468 Lecture 2423 Boundary Scan MUX
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ELEN 468 Lecture 2424 Integrated Serial Scan SFF Combinational logic PI PO SCANOUT SCANIN Control
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