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Implementation and Extensibility of an Analytic Placer Andrew B. Kahng and Qinke Wang UCSD CSE Department {abk, Work partially supported.

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Presentation on theme: "Implementation and Extensibility of an Analytic Placer Andrew B. Kahng and Qinke Wang UCSD CSE Department {abk, Work partially supported."— Presentation transcript:

1 Implementation and Extensibility of an Analytic Placer Andrew B. Kahng and Qinke Wang UCSD CSE Department {abk, qiwang}@cs.ucsd.edu Work partially supported by Cadence Design Systems, Inc., the California MICRO program, the MARCO Gigascale Silicon Research Center, NSF MIP-9901174 and the Semiconductor Research Corporation.

2 Motivation Automated placement: always critical –new challenges: larger design sizes, shorter turnaround times, a variety of additional physical and geometrical constraints, etc. New analytical methods: simultaneously spread cells and optimize wirelength –force-directed placement [Eisenmann et al. 98] –cell attracting and repelling (ARP) [Etawil et al. 99] Problem: wirelength is easily damaged by improper forces and attractors

3 Our Contribution A novel objective function for spreading cells is proposed recently [Naylor et al. 01] We implement an analytic placer (APlace) based on this idea –study characteristics of the objective function –extend the objective function with congestion information –implement a top-down multi-level placer: WL outperforms that of QPlace, Dragon and Capo –extend the placer to perform I/O-core co-placement for area-array I/O designs –extend the placer with constraint handling for mixed- signal designs

4 Outline Problem Formulation Implementation & Results Extensions Conclusion and Ongoing Work

5 Outline Problem Formulation –cell spreading = density control –wirelength minimization Implementation & Results Extensions Conclusion and Ongoing Work

6 Cell Spreading (I) Common strategy –divide the placement area into grids –equalize the total cell area in each grid Penalty of an uneven cell distribution –not smooth or differentiable –difficult to optimize

7 Cell Spreading (II) A bell-shaped cell potential function [Naylor et al. US Patent 2001] Cell c has potential(c, g) with respect to grid g Cell c at (CellX, CellY) has area A Grid point g = (GridX, GridY) p(d) : bell-shaped function r : the radius of cells' potential C : a proportionality factor, s.t. r 1-2d 2 /r 2 2(r-d) 2 /r 2 r/2 r d p(d)

8 Cell Spreading (III) Penalty function –conjugate gradient solver –stop when max movement of any cell between iterations is small –Discrepancy(A) –max ratio of actual total cell area to expected cell area over all windows with area A –measure evenness of cell distribution –disc = Discrepancy(1% area) EXPERIMENT: Cell distribution results with different number of grids and cell potential radii (r's) for the ibm01-easy circuit.

9 Outline Problem Formulation –cell spreading = density control –wirelength minimization Implementation & Results Extensions Conclusion and Ongoing Work

10 Wirelength Formulation (I) Linear vs. quadratic objective functions Approximation of linear objectives –precise –continuously differentiable Previous works –Gordian-L objective [Sigl et al. 91] –α-order objective function [Lillis et al. 95] –convex approximations of HPWL [Alpert et al. 98] [Baldick et al. 99] [Kennings and Markov 00]

11 Wirelength Formulation (II) Approximation of HPWL [Naylor et al. 01] –log-sum-exp formula: pick the most dominant terms among pin coordinates –  : smoothing parameter

12 Wirelength Formulation (III) Experiments –init HPWL = 7.311 –300 iterations –α smaller  wirelength formulation more accurate –α larger  WL minimized more quickly, and smaller final HPWL EXPERIMENT: Wirelength minimization results with different smoothing parameters (α's) for the ibm01-easy circuit. gridsalphainit WLfinal HPWL 1033367.5330.803 2016687.3690.836 3011127.3370.913 408347.3261.274 506677.3211.400 605567.3181.499 704767.3161.583 804177.3151.653 903707.3141.712 100333.67.3141.764

13 Outline Problem Formulation Implementation & Results –Conjugate gradient optimizer –Control factors –Top-down hierarchical algorithm –Placement results Extensions Conclusion and Ongoing Work

14 Conjugate Gradient Optimizer A series of line minimizations –one-dimensional function minimization along some search direction g k : the gradient  f(x k ) d k : the search direction s k : a step length obtained by a Golden Section search algorithm  k : ensures that d k is the conjugate direction when the function is quadratic and the line search finds the exact minimum along the direction –Polak-Ribiere formula

15 Control Factors Weights of wirelength and density objectives –density weight larger: spread the cells out hastily without a good wirelength –wirelength weight larger: contract cells together and prevents them from spreading out

16 Control Factors Weights of wirelength and density objectives –density weight: fixed larger: spread the cells out hastily without a good wirelength –wirelength weight larger: contract cells together and prevents them from spreading out set to be large in the beginning divided by 2 when the solver slows down and an optimal solution appears repeat until cells are spread evenly over the placement area #grids –coarser grids at the beginning: spread out the cells faster –finer grids at the final stages: a more even distribution

17 Top-Down Multi-Level Algorithm A hierarchy of clusters –MLPart [Caldwell et al. 99] Coarse grid: average cluster size Density penalty –regard each cluster as a macro cell –area of the macro cell = total area of the cluster Wirelength –cells: at center of clusters

18 Discrepancy and Wirelength Discrepancy as a function of iterations for the ibm01-easy circuit. HPWL as a function of iterations for the ibm01-easy circuit.

19 Placement Process Iter 100 –WL: 4.06E5 –disc: 10.69 Iter 200 –WL: 5.05E5 –disc: 4.17 Iter 300 –WL: 4.04E5 –disc: 2.53 Iter 400 –WL: 4.31E5 –disc: 1.86

20 Legalization A simple Tetris legalization algorithm [Hill 02] –sort cells according to vertical coordinates –from left to right, search the current nearest available position for each cell –fast –increases WL by 5% on average for IBM- PLACE 2.0 circuits Orientation optimization and row ironing [UCLApack]

21 Placement Results Comparison (HPWL) –Cadence QPlace (SE5.4): 9.0% (4.5% ~ 12.7%) –UCLA Dragon (2002): 4.8% (-6.5% ~ 10.2%) –Capo (v8.7): 8.7% (5.7% ~ 11.4%) Comparison (Running Time) –Xeon server (2.4GHz CPU, double-threaded) –faster than Dragon (0.8X), much slower than Capo (13.2X) Placement results of APlace for eight IBM-PLACE 2.0 circuits. QPlaceDragonCapo cktscellsnetsWL_l WLWL_ldisciterCPU (m) ibm01_easy 1228211507 0.590.57 0.480.521.19 1098 12.6 ibm01_hard 1202811507 0.560.550.560.460.501.18 1006 21.2 ibm02_easy 1932118429 1.561.60 1.411.451.12 1097 30.3 ibm02_hard 1906218429 1.521.471.561.381.441.11 1208 32.5 ibm07_easy 4513544394 3.723.663.713.173.291.14 968 63.8 ibm07_hard 4481144394 3.703.443.563.093.241.15 968 50.8 ibm08_easy 5097747944 3.953.613.933.513.651.11 887 75.4 ibm08_hard 5067247944 3.853.453.903.453.681.11 806 55.3 IBM-Place 2.0Aplace 1.0

22 Outline Problem Formulation Implementation & Results Extensions –Congestion-directed placement –IO-core co-placement –Constraint handling Conclusion and Ongoing Work

23 Accurate bend-based congestion estimator [Kahng and Xu, SLIP-03] Congestion-directed placement –ExpPotential(g) expected total potential at grid point g reduced, if g is congested  : congestion adjustment factor Congestion-Directed Placement (I)

24 Congestion-Directed Placement (II) Experiments –routability WL in gcell grid # over-capacity gcells –routability 38% better with  = 0.05 –routability deteriorates with larger  Placement and global routing results with varying congestion adjustment factors (  's) for the ibm01-hard circuit.

25 Experimental Results Comparison (Routed WL) –Cadence QPlace (SE5.4): 8.2% –UCLA Dragon (2002): 4.2% –Capo (v8.7): 10.4% With orientation optimization and row ironing –Cadence QPlace (SE5.4): 12.0% –UCLA Dragon (2002): 8.1% –Capo (v8.7): 14.1% Placement and routing results of APlace for eight IBM-PLACE 2.0 circuits with comparison to QPlace, Dragon and Capo. Placer WLCPUviolationsWLviasCPUWLCPUviolationsWLviasCPU ibm01eQPlace0.59300.8413856358ibm07eQPlace3.721204.6157251298 Dragon0.572700.8614130460Dragon3.666504.58569087103 Capo0.5715870.851467061446*Capo3.717424.93599806996 APlace0.532300.75139134100APlace3.306803.9953296374 ibm01hQPlace0.56300.8013859382ibm07hQPlace3.701205.04617942184 Dragon0.552600.8013999390Dragon3.4466154.63606561135 Capo0.56110290.841737151446*Capo3.56817995.146314561483* APlace0.512200.7113874582APlace3.265504.1054739896 Ckts Routing Placement

26 I/O-Core Co-Placement Peripheral I/O –constrained clock/power distribution –coupling and power issues for off-chip signaling Area-array I/O –improved pad count and reliability –reduced noise coupling Simultaneous I/O and core placement –I/Os are spread over the placement area, in the same way and at the same time as core cells –DensityWeight * DensityPenalty + IODensityWeight * IODensityPenalty

27 I/O-Core Co-Placement Results Randomly select 400 or 1000 cells and regard them as I/Os I/Os: distributed fairly evenly WL, disc of core cell distribution, and running times: not seriously impaired I/O-core co-placement results with different number of I/Os. I/O-core co-placement with 400 I/Os for ibm01-easy circuit.

28 Placement with Geometric Constraints Mixed-signal ASIC designs: parasitic effects –a large number of constraints Constraints in APlace: convert to penalty functions –alignment constraint, e.g. –spacing constraint, e.g. –axial symmetry, e.g. –nodal symmetry, e.g.

29 Constraint Handling Results Average WL increase: 8.2% Blue: Alignments Red: Nodal Symmetries + Spacing Black: Axial Symmetries + Spacing Placement results of APlace with 90 artificial geometric constraints. Placement of APlace with 90 artificial geometric constraints for ibm01-easy circuit. IBM-Dragon CktsWLWL_ldisciterCPU (m) ibm01e0.540.571.17 1309 57.3 ibm02e1.501.551.10 1208 70.2 ibm07e3.363.481.16 1049 122.8 ibm08e3.783.991.12 887 129.9 APlace with Constraints

30 Conclusion and Ongoing Work Implemented and conducted in-depth analysis of characteristics and results of APlace –placed and routed wirelengths outperform QPlace, Capo and Dragon. Extended the basic formulation –top-down hierarchical placement, congestion- directed placement, I/O-core co-placement, and constraint handling Ongoing work: –timing-driven placement –mixed-size placement

31 Prof. C.-K. Cheng, UCSD Bo Yao, UCSD Prof. Igor Markov, Michigan Saurabh Adya, Michigan Shubhyant Chaturvedi, Michigan Prof. C.-K. Koh, Purdue Chen Li, Purdue Prof. Andrew Kennings, Waterloo Thanks

32 Thank You !


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