1. Week 11b, Slide 1EECS42, Fall 2005Prof. White Week 11b OUTLINE – Synthesis of logic circuits – Minimization of logic circuits Reading: Hambley Ch. 7 through 7.6

2. Week 11b, Slide 2EECS42, Fall 2005Prof. White Combinational Logic Circuits Logic gates combine several logic-variable inputs to produce a logic-variable output. Combinational logic circuits are “memoryless” because their output value at a given instant depends only on the input values at that instant. Next time, we will study sequential logic circuits that possess memory because their present output value depends on previous as well as present input values.

3. Week 11b, Slide 3EECS42, Fall 2005Prof. White Boolean Algebra Relations AA = A AA = 0 A1 = A A0 = 0 AB = BA A(BC) = (AB)C A+A = A A+A = 1 A+1 = 1 A+0 = A A+B = B+A A+(B+C) = (A+B)+C A(B+C) = AB + AC AB = A + B De Morgan’s laws

4. Week 11b, Slide 4EECS42, Fall 2005Prof. White Boolean Expression Example F = ABC + ABC + (C+D)(D+E) F = C(A+D+E) + DE

5. Week 11b, Slide 5EECS42, Fall 2005Prof. White Logical Sufficiency of NAND Gates If the inputs to a NAND gate are tied together, an inverter results From De Morgan’s laws, the OR operation can be realized by inverting the input variables and combining the results in a NAND gate. Since the basic logic functions (AND, OR, and NOT) can be realized by using only NAND gates, NAND gates are sufficient to realize any combinational logic function.

6. Week 11b, Slide 6EECS42, Fall 2005Prof. White Logical Sufficiency of NOR Gates Show how to realize the AND, OR, and NOT functions using only NOR gates Since the basic logic functions (AND, OR, and NOT) can be realized by using only NOR gates, NOR gates are sufficient to realize any combinational logic function.

7. Week 11b, Slide 7EECS42, Fall 2005Prof. White Suppose we are given a truth table for a logic function. Is there a method to implement the logic function using basic logic gates? Answer: There are lots of ways, but one simple way is the “sum of products” implementation method: 1)Write the sum of products expression based on the truth table for the logic function 2)Implement this expression using standard logic gates. We may not get the most efficient implementation this way, but we can simplify the circuit afterwards… Synthesis of Logic Circuits

8. Week 11b, Slide 8EECS42, Fall 2005Prof. White Example: the half adder and the full adder AB Carry Sum A n+1 B n+1 C n+1 S n+1 CnCn SnSn AnAn BnBn C n-1

9. Week 11b, Slide 9EECS42, Fall 2005Prof. White S 1 using sum-of-products: 1)Find where S 1 is 1 2)Write down each product of inputs which create a 1 3)Sum all of the products 4)Draw the logic circuit Logic Synthesis Example: Adder ABCS1S1 S0S0 00000 00101 01001 01110 10001 10110 11010 11111 InputOutput A B C A B C + A B C

10. Week 11b, Slide 10EECS42, Fall 2005Prof. White NAND Gate Implementation De Morgan’s law tells us that is the same as By definition, is the same as  All sum-of-products expressions can be implemented with only NAND gates.

11. Week 11b, Slide 11EECS42, Fall 2005Prof. White Creating a Better Circuit What makes a digital circuit better? Fewer number of gates Fewer inputs on each gate –multi-input gates are slower Let’s see how we can simplify the sum-of- products expression for S 1, to make a better circuit… –Use the Boolean algebra relations

12. Week 11b, Slide 12EECS42, Fall 2005Prof. White Karnaugh Maps Graphical approach to minimizing the number of terms in a logic expression: 1.Map the truth table into a Karnaugh map (see below) 2.For each 1, circle the biggest block that includes that 1 3.Write the product that corresponds to that block. 4.Sum all of the products A B 2-variable Karnaugh Map 01 1 0 A 1 0 BC 00011110 3-variable Karnaugh Map 4-variable Karnaugh Map CD 00011110 AB 00 01 11 10

13. Week 11b, Slide 13EECS42, Fall 2005Prof. White ABCS1S1 S0S0 00000 00101 01001 01110 10001 10110 11010 11111 InputOutput 00011110 00010 10111 A BC AC AB S 1 = AB + BC + AC Simplification of expression for S 1 : Karnaugh Map Example

14. Week 11b, Slide 14EECS42, Fall 2005Prof. White Further Comments on Karnaugh Maps The algebraic manipulations needed to simplify a given expression are not always obvious. Karnaugh maps make it easier to minimize the number of terms in a logic expression.

15. Week 11b, Slide 15EECS42, Fall 2005Prof. White Homework Assignment 9 -- LogicWorks This 40-point assignment is to simulate one stage of a full adder using the LogicWorks program available on Windows machines in 199 Cory. Use your EE43 account log-in and password, or use this temporary log-in: ee42-temp pwd: Go Bears 005 Print out your circuit and the timing diagram and hand them in Thursday April 21 in the usual homework box. To help the grader, put “bus bars” with A and B and their complements on your circuit as shown on the next page here. There’s a LogicWorks manual/tutorial on those machines. Note: on your display be sure “show Window’s contents while dragging” is disabled. Your GSI has floppies you can use to store your work (temp account won’t allow machine storage). You can print your work on the printer in 199 Cory. If the Control bar doesn’t appear when you launch LogicWorks, on the Main toolbar at the top of the screen, click on Tools and then on Simulate.

16. Week 11b, Slide 16EECS42, Fall 2005Prof. White Two sets of “bus bars” on left provide variables and their complements for whatever you connect on the right side. Homework 9 -- continued

17. Week 11b, Slide 17EECS42, Fall 2005Prof. White Homework 9 -- concluded a. Draw and run your circuit as derived from the sum-of-products expressions for your sum and carry outputs using whatever gates you require. b.Then try to simplify those expressions using Boolean algebra. c.Then simply if possible using Karnaugh maps. d.Then draw the simplified circuit using whatever gates you need. e.How do you think the simplification has reduced the amount of space and number of transistors needed to make the full adder stage (qualitative answer acceptable)? Note: We could go further and realize the circuits entirely with NAND gates and obtain a quantitative answer, since we’ve already seen what transistors are inside a NAND gate in the Slide 6 of Week 10b, reprinted on next slide here.

18. Week 11b, Slide 18EECS42, Fall 2005Prof. White CMOS NAND Gate ABF 001 011 101 110 A F B AB V DD