1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 1 - Course Overview Fall 2008 Lab this week: meet at start of lab in AEC 429 See ECE 491 Moodle page for course materials Reading: Salt & Rothery Ch. 1 “Structural Design with Verilog” Sections 1-4

2. ECE 491 Fall 2008Lecture 1 - Course Overview2 Today’s Outline  Course Goals   Administrative Details  About Design  Problem Description

3. ECE 491 Fall 2008Lecture 1 - Course Overview3 Course Objectives  Understand the “Design Process: 1. The steps of the electronic “design process”. 2. The impact of constraints on design. 3. The organization of design teams. 4. Common tools for project management. 5. Economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability concerns.  Design with FPGAs and Verilog: 1. Understand the general structure of FPGAs 2. Understand the basic constructs of Verilog HDL. 3. Write Verilog code for combinational logic, sequential logic, and FSMs. 4. Write a Verilog testbench that verifies the correctness of a design. 5. Recognize and avoid common Verilog coding pitfalls. 6. Understand timing of digital systems in FPGA-based systems. 7. Understand the purpose of synchronizers in sequential logic designs. 8. Understand handshaking between sequential circuits w/ different clocks.

4. ECE 491 Fall 2008Lecture 1 - Course Overview4 Course Objectives (cont’d)  Understand Data Communications/Networking Concepts: 1. Asynchronous serial communications. 2. Manchester Code. 3. Ethernet and WiFi. 4. The Open Systems Interconnect (OSI) Model.

5. ECE 491 Fall 2008Lecture 1 - Course Overview5 Key Course Topics  FPGA-based Design with Verilog HDL  Data Communications and Networks  Engineering Design  The Design Process  Constraints and Tradeoffs  Design Verification  Project Management  Economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability concerns

6. ECE 491 Fall 2008Lecture 1 - Course Overview6 Today’s Outline  Course Goals  Administrative Details   About Design  Problem Description

7. ECE 491 Fall 2008Lecture 1 - Course Overview7 Administrative Details  Weekly Schedule (Day)  Mon., Wed.Lectures on Verilog/FPGA/Networks  TuesdayLab  FridayDesign Discussion, Quiz (sometimes)  Grading  Laboratory30%  Project 30%  Quizzes & HW20%  Final Exam20%  Warning: Labs and project will require work outside scheduled class & lab time!

8. ECE 491 Fall 2008Lecture 1 - Course Overview8 Academic Expectations in the Lab  Attendance required  All students in a group are expected to contribute  Groups must work independently  It’s OK to discuss strategies & general approaches  It’s not OK* to share code or simulation results  Groups must meet design deadlines for full credit  Late penalty: 10% / day *“not OK” == “academic dishonesty”

9. ECE 491 Fall 2008Lecture 1 - Course Overview9 Today’s Outline  Course Goals  Administrative Details  About Design   The Course Project

10. ECE 491 Fall 2008Lecture 1 - Course Overview10 What is Engineering Design? “Engineering design is the process of devising a system, component, or process to meet desired needs. It is a decision-making process (often iterative), in which the basic sciences, mathematics, and the engineering sciences are applied to convert resources optimally to meet these stated needs.” -- ABET Criteria for Accrediting Engineering Programs “An engineer is someone who can build for a dollar what any damn fool can build for ten” -- Robert A. Heinlein

11. ECE 491 Fall 2008Lecture 1 - Course Overview11 Some Characteristics of Design:  Open-ended  Subject to conflicting constraints (not just cost)  Must generally conform to existing standards  Requires tradeoffs  Iterative  Usually a team activity  Analysis & verification essential to success  Sophisticated planning and management needed

12. ECE 491 Fall 2008Lecture 1 - Course Overview12 Design Constraints  Some Common Constraints  Cost  Performance  Environmental  Manufacturability  Sustainability  Social  Political  Legal  Ethical  Health and safety

13. ECE 491 Fall 2008Lecture 1 - Course Overview13 The Design Process  Usually defined as a sequence of steps  Several models are used  “Systematic Model of Design” e.g., S&R  Colwell’s model in The Pentium Chronicles  Software Design Models “Waterfall Model” - SW version of “Systematic Model” Rapid Prototyping / “Extreme Programming” Model

14. ECE 491 Fall 2008Lecture 1 - Course Overview14 Example: The S&R Design Process  Requirements analysis  Creating a detailed problem specification  Defining what is needed for completion  System Design  Determine “how problem will be solved”  Create a system specification that describes design at a functional level  Result: detailed spec, block diagrams  Detailed Design  Create designs for blocks in system design  Debug and verify individual blocks  System Integration and Test  Combine design blocks  Test complete system Customer needing solution to a problem Properly functioning system S&R Figure 2.4 Requirements analysis System design Detailed design System Integration And Test

15. ECE 491 Fall 2008Lecture 1 - Course Overview15 Design Process Models - Key Points  A model only approximates what really happens  Brooks: Conceptual Integrity is major challenge  Non-trivial projects require large teams  Communication of design to team members is essential  “Great designs are created by great designers”  Design errors are inevitable - need to:  Anticipate (and look for) errors  Avoid the needless creation of errors  Deal with errors as they occur  Tools for dealing with errors: Verification (Simulation, Lab Testing) Design Reviews

16. ECE 491 Fall 2008Lecture 1 - Course Overview16 How We’ll Learn About Design  By example  S&R text - general theory, project management  Colwell “At Random” columns from IEEE Computer  Brooks Turing Award Lecture “The Design of Design”  Costello DAC ‘06 Lecture: “Iridium or iPod…”  By doing  ECE 491: small-group design of a wireless network  ECE 492: large-group design of a solar power system

17. ECE 491 Fall 2008Lecture 1 - Course Overview17 Today’s Outline  Course Goals  Administrative Details  About Design  The Course Project 

18. ECE 491 Fall 2008Lecture 1 - Course Overview18 The Course Project  Design a wireless local-area network so that each “station” can communicate with other station Stations

19. ECE 491 Fall 2008Lecture 1 - Course Overview19 Course Project - Key Questions 1.What physical link will we use? 2.How will we transmit data? (transmission) 3.How will stations cooperate to send and receive data? (protocol) 4.How can we break up the problem to make it tractable? 5.How will we implement the system?

20. ECE 491 Fall 2008Lecture 1 - Course Overview20 1. Physical Link Options  Wired  Fiber Optics  Wireless - Optical  Wireless - Microwave  Wireless - VHF Radio

21. ECE 491 Fall 2008Lecture 1 - Course Overview21 2. Transmission Options  Wired  Single-ended  Differential  Carrier  Wireless  ASK - Amplitude Shift Keying  FSK - Frequency Shift Keying  PSK - Phase Shift Keying  QAM - Quadrature Amplitude Modulation  Spread Spectrum

22. ECE 491 Fall 2008Lecture 1 - Course Overview22 3. Protocol  A set of rules for communication over a network  Often standardized to allow interoperable hardware from different vendors  Ethernet - IEEE 802.3  Wireless - IEEE 802.11

23. ECE 491 Fall 2008Lecture 1 - Course Overview23 4. Implementation Options  Use existing hardware (e.g., PC + WiFi card)  TTL Packages on a PCB or Breadboard  Microcontroller plus serial interface  Programmable Logic Devices  PALs / GALs  FPGAs  Application-Specific Integrated Circuit (ASIC)  Custom Integrated Circuit

24. ECE 491 Fall 2008Lecture 1 - Course Overview24 Our Design Approach Network Interface Buffer Memory (Block RAM) Spartan3 Board XC2S300 FPGA Transmitter Back End Test Interface PC RS-232 Buffers Receiver Front End

25. ECE 491 Fall 2008Lecture 1 - Course Overview25 Project Summary  Each lab group will design a WLAN station  Network Design: Simplified protocol based on Ethernet and 802.11  Grading Criteria  For a “C” project grade, must demonstrate: Communication between two copies of your station via wire Communication with stations designed by other groups  For an “A” project grade, must also demonstrate Working CRC error detection Working ACK / backoff mechanism (more about this later)

26. ECE 491 Fall 2008Lecture 1 - Course Overview26 Project Schedule

27. ECE 491 Fall 2008Lecture 1 - Course Overview27 Coming Up:  FPGA Review  Spartan Board Quick Intro  Digital Design with Verilog  Combinational Design  Sequential Design