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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 12 - System Design & Project Mgt. Fall 2006 Reading: S&R Ch.4 - System Design S&R Ch. 5 - Project Management Colwell Ch. 2 - The Concept Phase Colwell Ch. 3 - The Refinement Phase
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ECE 491 Fall 2006Lecture 12 - System Design2 Where we are Last Time: Timing Metastability Today: System Design Project Management P6 System Design / Project Management
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ECE 491 Fall 2006Lecture 12 - System Design3 Review: S&R Design Methodology Requirements analysis Creating a detailed problem specification Defining what is needed for completion System Design Determine “how problem will be solved” Create a system specification that describes design at a functional level Result: System specification Detailed Design Create designs for blocks in system design Debug and verify individual blocks System Integration and Test Combine design blocks Test complete system Customer needing solution to a problem Properly functioning system S&R Figure 2.4 Requirements analysis System design Detailed design System Integration And Test
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ECE 491 Fall 2006Lecture 12 - System Design4 The System Design Process S&R Figure 4.4 Development of Concepts Analysis Synthesis Requirements Specification System Specification Reject Unworkable Concepts
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ECE 491 Fall 2006Lecture 12 - System Design5 Key Steps - Conceptualization Goal - develop “hazy perception of a solution” Sources of concepts Draw from solutions to similar problems Come up with original solution based on prior experience Brainstorming sessions - see Colwell Ch. 2
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ECE 491 Fall 2006Lecture 12 - System Design6 Key Steps - Synthesis Goal - “bring structure to the initial concept”; provide detail needed for analysis & implementation Block diagram as the key Start out with a “rough sketch” Add detail as design proceeds Refine as design proceeds
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ECE 491 Fall 2006Lecture 12 - System Design7 Block Diagram Guidelines Each block should be implementable with a single technology Common functions should be grouped into one block Blocks should be defined to simplify interfaces Avoid feedback loops if possible Specify assertion levels in digital interfaces Specify characteristics (e.g., impedance, frequency) of analog & RF interfaces Anticipate difficulty in timing and sequencing of interface signals
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ECE 491 Fall 2006Lecture 12 - System Design8 Example - Flicker Analyzer Initial Block Diagram Voltage divider by 75 Anti- aliasing filter 2.5 8-bit A/D converter Oscillator 200 Hz square clock for sampling RS 232 19.2 kbps no parity To the serial port of the PC Ground Common Chassis S&R Figure 4.8 A/D input range Is 0 to 5 volts Between +/- 2.5 Neutral v(t)
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ECE 491 Fall 2006Lecture 12 - System Design9 Example - Flicker Analyzer Refined Block Diagram Voltage divider 75 +/-.5% Anti- aliasing filter 1 +/-.5% 2.5 +/- 0.18 16-bit A/D converter Oscillator 200 Hz square clock for sampling RS 232 3 bytes per sample Ground Common Chassis S&R Figure 4.9 16-bit bus 16-bit A/D converter Neutral v(t)
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ECE 491 Fall 2006Lecture 12 - System Design10 Key Steps - Analysis Goal - determine if synthesized system will meet performance and cost objectives Secondary goal - determine risk of completing design Tools for analysis Mathematical models Simulations - Verilog, Matlab, Simulink, etc. Lab-based prototype
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ECE 491 Fall 2006Lecture 12 - System Design11 End Product - The System Specification Summary of the Concept Annotated Block Diagram, I/O specification Functional descriptions of blocks System description System analysis - results of analysis, simulation, measurements
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ECE 491 Fall 2006Lecture 12 - System Design12 System Design on the P6 A Data-Driven Culture The problem: intuition is often wrong and differs widely between engineers The solution: design and conduct small experiments and collect data about issue in question A tradeoff Too much analysis will impede progress Too little will result in a poor design
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ECE 491 Fall 2006Lecture 12 - System Design13 P6 Analysis Tools The Data Flow Analyzer (DFA) - a tool to evaulate parallelism Input: execution traces, constraints Output: expected speedup RTL Simulator
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ECE 491 Fall 2006Lecture 12 - System Design14 Project Management - What is a Project? Quantifiable piece of work Defined start and end Expectation of specific outputs and deliverables Measurable objectives Limited Resources (people, materials, equipment) Often complex, uncertain, and/or urgent
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ECE 491 Fall 2006Lecture 12 - System Design15 Elements of Project Management Planning Define work to be done Develop schedule to complete work Develop budget Specify needed resources (materials, people, equipment) Monitoring Keep track of project Determine whether deadlines will be met Control Shift resources between tasks Modify plan to optimize progress
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ECE 491 Fall 2006Lecture 12 - System Design16 The Project Plan Definition of Work Schedule Resource requirements Cost estimate
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ECE 491 Fall 2006Lecture 12 - System Design17 S&R Fig. 5.2 The Planning Process System design Detailed design Preliminary plan Define work Develop schedule Estimate resources Estimate costs Design Mgt. Project plan Design ProcessPlanning Process
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ECE 491 Fall 2006Lecture 12 - System Design18 Definition of Work Use system design, block diagram as info source Develop a list of tasks to be completed Describe the deliverables of each task Document any needed inputs Specify completion date needed (“milestone”) Estimate duration Estimate resources needed Determine precedence w.r.t. other tasks Example: See S&R Tables 5.1 - 5.3
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ECE 491 Fall 2006Lecture 12 - System Design19 Scheduling Goal: determine order in which tasks are performed Scheduling diagrams Network diagrams Bar Charts (Gantt Charts)
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ECE 491 Fall 2006Lecture 12 - System Design20 Network Diagram Activity on Arrow (AOA) 03789.51 System Design (3) Power supply (1) Main board (4) Packaging (3) Integrate and test(1) Finalize (1.5) Prototype (1.5) EndStart S&R Fig. 5.4
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ECE 491 Fall 2006Lecture 12 - System Design21 Network Diagrams Activity on Node (AON) 1.03.0 System Design 003 3.02.5 Pwr supply 33.04 5.01.0 Integrate & Test 708 6.01.5 Finalize 809.5 7.01.5 Prototype 9.5011 4.03.0 Packaging 31.06 2.04.0 Main board 307 8.011.0 Packaging 0011 Task no.Elapsed Time. Start Week Slack Time End Week S&R Fig. 5.5
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ECE 491 Fall 2006Lecture 12 - System Design22 Bar Charts (Gantt Charts) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 System design Main board design Power supply design Packaging design Integrate & test Finalize design Construct prototypes Project management 010815222906132027031017 01 Start Finalize System Design Complete Acceptance Test Design Signoff End S&R Fig. 5.7
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ECE 491 Fall 2006Lecture 12 - System Design23 Scheduling Tools Microsoft Project Primavera GanttProject – Open Source Java program (available at ganttproject.sourceforge.net)
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ECE 491 Fall 2006Lecture 12 - System Design24 GanttProject - Gantt Chart View
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ECE 491 Fall 2006Lecture 12 - System Design25 GanttProject - Network Diagram View
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ECE 491 Fall 2006Lecture 12 - System Design26 Cost Estimation Personnel Direct costs - Wages Indirect costs (Overhead) – Benefits, facilities costs, supporting departments, etc. Lab, shop, and other internal facilities Outside services and facilities Supplies and materials More details in S&R Section 5.5
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ECE 491 Fall 2006Lecture 12 - System Design27 Managing a Project Performance Monitoring Task Progress Schedule Status Budget Status Reporting
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ECE 491 Fall 2006Lecture 12 - System Design28 P6 Project Management Organizing a team: Make assignments to exploit strengths of each individual Put best engineers on “most difficult” parts of design Assign jobs based to give individual best “leverage” Provide leadership for new hires
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ECE 491 Fall 2006Lecture 12 - System Design29 P6 Design Team - Organization Colwell Fig. 2.3, p. 36
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ECE 491 Fall 2006Lecture 12 - System Design30 P6 Verification - “Presilicon Validation” Goal: test RTL model as it becomes available Ideal: “keep presilicon validation separate from, but embedded within, design team” Challenge: validators get “absorbed” as designers Approach: Module designers write basic “unit tests” Require “at least minimal” testing before release When integrating modules into larger units, debug using the “bigger wizard” approach
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ECE 491 Fall 2006Lecture 12 - System Design31 P6 Organization - Additional Notes The importance of physical proximity Place designers working on same unit in adjacent cubicles Place design groups on adjacent units nearby - cubicle floorplan mimics chip floorplan! Place architects in center to avoid “us vs. them” Bad idea: separating architects into a long-range R&D group
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ECE 491 Fall 2006Lecture 12 - System Design32 Coming Up Data Communications (cont’d) RS-232 Receiver Design Manchester Code Ethernet Detailed Design
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