1. Exploration of Pipelined FPGA Interconnect Structures Scott Hauck Akshay Sharma, Carl Ebeling University of Washington Katherine Compton University of Wisconsin - Madison

2. 2 PipeRoute FPGA’2003: Pipelining-aware Router for FPGAs Architecture-adaptive, based on Pathfinder Uses optimal 2-terminal, 1-delay router Greedy formulation for multi-delay, multi-terminal routing T1T1 S   T2T2

3. 3 RaPiD Coarse-grained, 1D, 16-bit, w/DSP Units Carl Ebeling @ UW-CSE Pipelined interconnect via Bus Connectors (BCs)

4. 4 Pipelined Routing Results Area expansion due to pipelining Normalized to unpipelined circuit area T S  T S Ave: 75% cost

5. 5 Contributions Optimized PipeRoute Support multiple delays per BC (greedy preprocessor) Timing driven – Pathfinder’s, worst-case criticality across signal RouteCost = Criticality * delay_cost + (1-criticality) * area_cost Arch. Exploration of RaPiD Pipelined Interconnects Registered logic block (input/output/none) BC track length Delays per register/BC BC/non-BC routing mix Register-only logic blocks Goal: More efficient support of pipelined interconnects TS  

6. 6 Methodology Benchmarks Retimed, not C-slowed Graphs Increase arch to fit (cells, tracks/cell) Variation around local minima

7. 7 Registers in Logic Blocks Output Registers No Registers Input Registers + +   + T1T1 S   T2T2 5% 20% 23%

8. 8 Delays per Register/BC 1 Delay/BC 2 Delays/BC  15% 20% 30%

9. 9 BC Track Length Length 16 BC wires Length 8 BC wires 17% 64% 69%

10. 10 Routing Resource Mix (BC vs. non-BC) 5/7 7/7 19% 17% 18%

11. 11 GPRs per Cell GPR roles: Registers from computation Passthrough for changing tracks 6 per cell 9 per cell 6% 23% 22%

12. 12 Overall – vs. RaPiD-I RaPiD-I 1 BC / cell (13 LBs long) 5/7 BC tracks 3 registers / BC 6 GPRs / cell registered outputs Post-Explore 1 BC / cell (16 LBs long) 5/7 BC tracks 3 registers / BC 9 GPRs / cell registered inputs Ave: 1% 18% 19%

13. 13 Overall – Pipelining Cost T S  T S Ave: 18% cost

14. 14 Conclusions Router for arbitrary pipelined architectures Timing-driven Supports multiple delays at each register site Good quality: <18% of pseudo-lower bound (non-pipelined) area Architecture Exploration of RaPiD Parameters: Registered inputs on functional units Length 16 wires 3 delays per BC/register 2/7 non-registered, 5/7 registered wires 9 GPRs/cell to improve flexibility Delay: spacing of registers CRITICAL, too close better than too far 19% area*delay improvement over RaPiD-I (primarily delay)

15. 15 *** End of Talk Marker ***

16. 16 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

17. 17 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

18. 18 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

19. 19 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

20. 20 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

21. 21 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

22. 22 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS  T S 

23. 23 N-Delay Two Terminal Greedy Approximation via 1-Delay Router  T S    

24. 24 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route  T S    

25. 25 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement  T S    

26. 26 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement  T S    

27. 27 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement  T S    

28. 28 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement  T S    