1. A New Network Processor Architecture for High-speed Communication Xiaoning Nie; Gazsi, L.; Engel, F.; Fettweis, G. Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on, 1999, Page(s): 548 -557

2. What ’ s the Problem The requirement of high-speed communication The requirement of a flexible software/hardware platform for protocol processing A Network Processor (NP) is then derived

3. Introduction The xDSL and cable modems provide 2 Mb/s for a person. Programmable and configurable hardware design need to be provided in system level requirement. A general purpose processor would waste portions of its processing power due to no use of its functionalities such as floating-point unit.

4. Seven Layers of OSI model Application Presentation Session Transport Network Data Link Physical TCP/IP Ethernet TELNET application

5. The Top-Level Architecture Host: (1) completes web- browsing or telnet sessions. (2) implements by one or several processors Adaption: (1) prepares the information for physical transmission and delivers the application- relevant information to the host layer. (2) implements by one processor. Media: (1) responses for reliable physical transmission and receiving of the information. (2) implements by hardwired manner or DSPs.

6. Router/Switch Adaption Media Host Transport Network Physical

7. What tasks are for the NP Deals with protocols that always contain some headers and the payloads. NP operations: The operations for data transfer (move, load, store, parse) consumes a significant portion of the processing power. There can be very frequent interrupts especially if the buffering has to be limited due to some network delay constraints e.g. in video communication applications. There are many operations involved in the finite state machines.

8. For routing/switching efficient access to some lookup tables is essential. Depending on the protocol, there can be many operations that are not word or even byte-aligned. What tasks are for the NP

9. Essential Characteristics for NP A fixed-point RISC based architecture No floating-point operations Data movement: register  port memory  port Example: move port1@ bit1 port2@ bit2

10. NP Architecture Separated memory buffer: (1) communication interface data (2) Software control data Zero-overhead, hardware-supported threads

11. Data Transfer Bit-operation: (load) LOAD dest@ bit source@ bit bit-width Data transfer runs in one thread in parallel to the other thread. Example: (store) /*start block move and let the task #task run in parallel*/ Repeat counter #task STORE_BL port@ bit dest@ bit number Saving registers for the management of the DMA controller.

12. Bit-manipulation Support Bit access, bit addressing Specifies bit-width, bit-offset Example: Ry.Oy := Ry.Oy AND Rx.Ox @ Width

13. Comparison between ARM and New NP

14. Loop Support by Compute & Jump Until R1=0, otherwise always jumps to L1

15. A “ For Loop ” Example for (i=0;i<10;i++) a[i]=11; 5 cycles 3 cycles Until R3=0, otherwise always jump to FOR

16. Conclusions Variable bit-width operations work efficiency, and reduce power consumption. Compound instructions help to reduce execution cycles of a program. Multi-thread hardwired hardware reduces register usage due to the requirement of DMA controller.