1. 1 3-Tap FIR Filter Optimizations By: Jeff Rybczynski CMPE 222

2. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski2 3-Tap FIR Filter Design

3. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski3 FIR Filter Control Six States meaning 3 bit State Variable Each Multiply is in a separate state Asynchronous Reset

4. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski4 FIR Filter Data Path 3 Independent Multiply Operations 3 Independent Addition Operations Not order dependent

5. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski5 Optimized FIR Control Take out extra calculate steps and place all the multiplies in one CALC state Add the values from the multiply step together in ADD state Place value directly into result before you raise output_ready

6. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski6 Changes to the Verilog Code 3'b100 : begin output_ready <= 1'b0; rin <= sample; end 3'b110 : acc <= rin * 24'h702a78; 3'b111 : acc <= rs0 * 24'h800000 + acc; 3'b101 : acc <= rs1 * 24'h4fd547 + acc; 3'b001 : begin output_ready <= 1'b1; result <= acc; rs1 <= rs0; rs0 <= rin; end default : begin acc <= 24'h000000; output_ready <= 1'b0; end Original Verilog Code

7. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski7 Changes to the Verilog Code Optimized Code 2'b00 : begin output_ready <= 1'b0; rin <= sample; end 2'b10 : begin temp1 <= rin * 24'h702a78; temp2 <= rs0 * 24'h800000; temp3 <= rs1 * 24'h4fd547; end 2'b11 : begin result <= temp1 + temp2 + temp3; rs1 <= rs0; rs0 <=rin; output_ready <=1’b1 end 2'b01 : output_ready <= 1'b0;

8. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski8 Array Multiplier Similar to how you multiply by hand Cascading Array multiplier blocks 6x6 Multiplier

9. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski9 Array Multiplier Block

10. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski10 Array Multiplier

11. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski11 Add Array Multiplier to Verilog Code New Code: array_multi a(temp1,rin, 24'h702a78); array_multi b(temp2,rs0, 24'h800000); array_multi c(temp3,rs1, 24'h4fd547); Old Code: temp1 <= rin * 24'h702a78; temp2 <= rs0 * 24'h800000; temp3 <= rs1 * 24'h4fd547;

12. Monday, June 02, 2003FIR Optimization – Jeff Rybczynski12 FIR Designs AreaTime Original FIR Design 77182.4531259.77 ns Optimized FIR 3 Latency 76806.578125 9.61 ns Optimized FIR Array Multiplier 91060.1875009.73 ns