1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 491 - Senior Design I Lecture 5 - Coding Guidelines; Simulation & Delay Fall 2007 Read Verilog Handout Section 7

2. ECE 491 Fall 2007Lecture 5 - Verilog Simulation2 Today’s Outline  Verilog Coding Guidelines  A brief aside: timing and clocks  Verilog Part 3  Simulation Basics of Event-Driven Simulation Delay Modeling  initial blocks  Functions  Tasks  System Tasks  Recent developments in Verilog

3. ECE 491 Fall 2007Lecture 5 - Verilog Simulation3 Verilog Coding Guidelines  Why bother with coding guidelines?  Try to avoid common errors and pitfalls Latch inferences Simulation/Synthesis mismatch Timing problems  Try to make designer’s intent clear To others who use your design s When you use or re-use your own designs

4. ECE 491 Fall 2007Lecture 5 - Verilog Simulation4 Verilog Coding Guidelines - 1  Use one file for each module.  Include a header block in each file that includes:  Your names  Brief description of module  History  Usage guidelines  Use “template” from ISE “Edit” menu  Use comments liberally.  Use meaningful signal names.  Be consistent using capitalization and underscores.  Properly indent your code, as shown in examples.

5. ECE 491 Fall 2007Lecture 5 - Verilog Simulation5 Verilog Coding Guidelines - 2  Partition your design into leaf cells and non-leaf cells.  Leaf cells contain assign statements or always blocks but do not instantiate other cells.  Non-leaf cells instantiate other cells but contain no logic. (Minor exceptions OK to keep the code readable.)  Use assign statements for comb. logic when practical.  Use only nonblocking (<=) assignments in always blocks that model sequential logic.  Use only blocking (=) assignments in always blocks that model combinational logic.  Avoid latch inferences in combinational always blocks!

6. ECE 491 Fall 2007Lecture 5 - Verilog Simulation6 Verilog Coding Guidelines - 3  Use only positive edge-triggered flip-flops for storage  Use symbolic constants (parameters) to define state names and constants  Use synchronizer flip-flops for asynchronous inputs  Keep number of separate clock signals to a minimum  When multiple clocks are used:  Don’t mix clocks - partition design into clock domains  Use synchronizer flip-flops when passing from one clock domain to another

7. ECE 491 Fall 2007Lecture 5 - Verilog Simulation7 Review - Flip-Flop Timing Characteristics  Propagation Delay t CQ  Setup time t setup  Hold time t h D Q clk D t setup thth CLK Q t CQ

8. ECE 491 Fall 2007Lecture 5 - Verilog Simulation8 What Limits Clock Frequency?  Propagation delay - t prop Logic (including register outputs) Interconnect  Register setup time - t setup Adder Mux Combinational Logic Register Output Register Input Clock t prop t setup t clock > t prop + t setup t clock = t prop + t setup + t slack

9. ECE 491 Fall 2007Lecture 5 - Verilog Simulation9 Timing in FPGA Design - Constraints  The constraints file specifies timing using the TIMESPEC directive #TIMESPEC = FROM : : TO : : ;  In the “s3board.v” file - using predefined groups # Time specifications for 50MHz clock # #TIMESPEC TS01 = FROM : FFS : TO : FFS : 20 ns; #TIMESPEC TS02 = FROM : RAMS : TO : FFS : 20 ns; #TIMESPEC TS03 = FROM : FFS : TO : RAMS : 20 ns; #TIMESPEC TS04 = FROM : RAMS : TO : RAMS : 20 ns; #TIMESPEC TS05 = FROM : FFS : TO : PADS : 20 ns; #TIMESPEC TS06 = FROM : PADS : TO : FFS : 20 ns; #TIMESPEC TS07 = FROM : PADS : TO : RAMS : 20 ns; #TIMESPEC TS08 = FROM : RAMS : TO : PADS : 20 ns;

10. ECE 491 Fall 2007Lecture 5 - Verilog Simulation10 Synchronizers  Key idea: make sure inputs don’t change at a “bad time” in sequential circuits in1 in2 in3 00 1001 in1’ in1 0110 clk in1 NS 11 transient

11. ECE 491 Fall 2007Lecture 5 - Verilog Simulation11 Adding Synchronizers  Add a D Flip-Flop on each asynchronous input  Synchronize each input only once DQ clk in2_a in2_s DQ in1_a in1_s

12. ECE 491 Fall 2007Lecture 5 - Verilog Simulation12 Single-Clock Sequential Logic  Clock arrives at all flip-flops simultaneously  Timing analysis verifies clock period constraints  But, not all systems use a single clock! a b c q always@(posedge clock) DQ clk

13. ECE 491 Fall 2007Lecture 5 - Verilog Simulation13 Dealing Multiple Clocks  Multiple clocks are not synchronized!  Must synchronize connecting signals a b c q always@(posedge clk1) DQ clk1 d e f r always@(posedge clk2) DQ clk2 clk1 clk2 DQ Synchronizer

14. ECE 491 Fall 2007Lecture 5 - Verilog Simulation14

15. ECE 491 Fall 2007Lecture 5 - Verilog Simulation15 Verilog and Event-Driven Simulation  Key idea: model circuit operation as sequence of events that take place at specific times  Input events - when input changes  Output events - response to input events (only generated when output changes) A B C A B C delay=4 input event output event

16. ECE 491 Fall 2007Lecture 5 - Verilog Simulation16 Event-Driven Simulation  Example: Modeling and AND Gate  Input events: changes on A, B input net  Output events: changes on C output net after delay A B C A B C t=5 A=1 t=17 B=1 t=33 B=0 t=29 C=1 delay=12 t=45 C=0 Input Events Output Events

17. ECE 491 Fall 2007Lecture 5 - Verilog Simulation17 Event-Driven Simulation  Output events from AND = input events for OR  Simulation time “jumps” from event to event A B C A B C delay=3 D E delay=4 D E

18. ECE 491 Fall 2007Lecture 5 - Verilog Simulation18 Notes about Event-Driven Simulation  Why use event-driven simulation? Because it's fast  Only model when signals change  Loss of accuracy: assumes ideal logical behavior  What are the alternatives?  Circuit simulation (e.g. PSpice) Numerical model of continuous behavior More accurate, but slower  Cycle-Level Compiled code simulation Model behavior in each clock cycle Faster, but doesn’t model delay

19. ECE 491 Fall 2007Lecture 5 - Verilog Simulation19 Event-Driven Simulation (cont'd)  Processing Events - Data Structures  Event - specifies time event will occur net where signal will change new value of net  Event Queue - data structure that sorts events by time front of queue - earliest event back of queue - latest event also called a timing wheel

20. ECE 491 Fall 2007Lecture 5 - Verilog Simulation20 Event-Driven Simulation - Algorithm  Processing Events - Simulation Algorithm initialization: set all nets & regs to ‘x’ while (event queue not empty) { current_event = "earliest" event in queue; current_time = current_event.time; current_event.net.value = current_event.value; for (each module input connected to net) { evaluate(module) if output of module changes { create new event to represent output change add new event to queue } } }

21. ECE 491 Fall 2007Lecture 5 - Verilog Simulation21 Verilog Simulation Model  assign statement  executes when event changes any input  produces output event when output values changes  always block  executes when event changes variable in sensitivity list  produces output events when outputs change assign y = ~a; always @(a or b) x = a ^ b;

22. ECE 491 Fall 2007Lecture 5 - Verilog Simulation22 Delays in Event-Driven Simulation  Two kinds of delays supported:  Inertial delays - reflects limited response time in real gates  Transport delays - try to model delay through a wire

23. ECE 491 Fall 2007Lecture 5 - Verilog Simulation23 Inertial Delays  What happens here? A B C A B C delay=t d t1t1 t2t2 tdtd t 2 - t 1 > t d A B C A B C delay=t d t1t1 t2t2 tdtd t 2 - t 1 < t d Event-driven model: Narrow Pulse Real gate: No change (why?)

24. ECE 491 Fall 2007Lecture 5 - Verilog Simulation24 Inertial Delays in Event-Driven Simulators  Each signal change is scheduled in event queue  When scheduling, compare to most recent change to calculate “pulse width”  If (pulse_width < prop_delay) deschedule both events 3 Delay = 2 5 4 6 De-scheduled Events 3 5911

25. ECE 491 Fall 2007Lecture 5 - Verilog Simulation25 Transport Delays  What happens here? A C delay=t d Long Wire B A B tdtd Change propagated independent of pulse width

26. ECE 491 Fall 2007Lecture 5 - Verilog Simulation26 Modeling Delays in Verilog  Delays in Structural Verilog  Gate primitives: inertial delays and #5 g1(o1, a, b);  Net delays (transport) wire #5 w1;  More complex modules: specify  Delays in Behavioral Verilog  assign statements assign #10 a = x & y;  always & initial blocks blocking delay #10 a = x +y; interassignment delay a = #10 x + y;

27. ECE 491 Fall 2007Lecture 5 - Verilog Simulation27 Structural Delay - Gate Primitives and G1 (y1, a, b); and #5 G2 (y2, a, b); and #(7,5) G3 (y3, a, b); and #(6:7:8,4:5:6) G4 (y4, a, b); buf_if1 #(6,5,2) B1 (y5, a, enb); // 3-state buf rising delayfalling delaysingle delay value rising delay min : typ : max falling delay min : typ : max no delay value (delay = 0)rising delayturnoff delay falling delay

28. ECE 491 Fall 2007Lecture 5 - Verilog Simulation28 Delay in assign statements  Delay specified as in structural specifications assign #5 y1 = a & b; assign (#4,#5,$6) y2 = a & b;  Specifies inertial delay

29. ECE 491 Fall 2007Lecture 5 - Verilog Simulation29 Delays in Behavioral Verilog - Blocking Delay  Delay control operator - #n  Simulation effect: suspends simulation for n time units  Example: clock generator always begin clk = 0; #50 clk = 1; #50 ; end null statement (suspends simulation 50 time units)

30. ECE 491 Fall 2007Lecture 5 - Verilog Simulation30 Delays in Behavioral Verilog - Interassignment Delay  Key idea: unlike blocking delay, RHS is evaluated before delay  With blocking assignments: a = #5 b + c; d = a;  With nonblocking assignments: a <= #5 b + c; d = a; b + c evaluated; change in a scheduled delayed until 5 time units elapse b + c evaluated; change in a scheduled executes immediately; gets OLD value of a!

31. ECE 491 Fall 2007Lecture 5 - Verilog Simulation31 Representing Time in Verilog  Verilog uses “dimensionless” time units  Mapping time units to “real” time: `timescale `timescale /  Examples `timescale 1ns / 1ps `timescale 10ns / 100ps  Each module can have a different timescale (but this is not necessarily a good idea!) Time Units of # Delay Values Minimum step time used by simulator

32. ECE 491 Fall 2007Lecture 5 - Verilog Simulation32 Simulation Time in Verilog: # and `timescale  `timescale controls simulation time `timescale time_unit time_precision `timescale 1ns 100ps  # operator specifies delay in terms of time units `timescale 1ns 100ps #5 // delays 5*1ns = 5ns; // rounds times to 100ps `timescale 4ns 1ns #3 // delays 3*4ns = 12ns // rounds times to 1ns

33. ECE 491 Fall 2007Lecture 5 - Verilog Simulation33 What happens when no delays are specified?  Each output event has a “delta” delay  Events processed in order of scheduling

34. ECE 491 Fall 2007Lecture 5 - Verilog Simulation34 initial statements  Specify code to be executed on simulation startup initial sequential_statement  Not supported in synthesis - tell synthesis to ignore using synthesis directives (“pragmas”)  Very useful in testbenches! // synthesis translate_off initial begin … code to generate input stimulus & check outputs end // synthesis translate_on Synthesis Directive

35. ECE 491 Fall 2007Lecture 5 - Verilog Simulation35 Verilog functions  Function Declaration: function [ range_or_type ] fname; input_declarations statement endfunction  Return value: function body must assign: fname = expression;  Function call: fname ( expression,… )

36. ECE 491 Fall 2007Lecture 5 - Verilog Simulation36 Verilog Functions (cont'd)  Function characteristics:  returns a single value (default: 1 bit)  can have multiple input arguments (must have at least one)  can access signals in enclosing module  can call other functions, but not tasks  cannot call itself (no recursion)  executes in zero simulation time (no timing ops allowed)  Synthesized as combinational logic (if proper subset is used)

37. ECE 491 Fall 2007Lecture 5 - Verilog Simulation37 Verilog Functions (cont'd)  Function examples: function calc_parity; input [31:0] val; begin calc_parity = ^val; end endfunction function [15:0] average; input [15:0] a, b, c, d; begin average = (a + b + c + d) >> 2; end endfunction;

38. ECE 491 Fall 2007Lecture 5 - Verilog Simulation38 Verilog Tasks  Similar to procedures in VHDL, Pascal  Multiple input, output, and inout arguments  No explicit return value (use output arguments instead)  No recursion allowed  Can "enable" (call) other tasks and functions  May contain delay, event, and timing control statements (but not in synthesis)

39. ECE 491 Fall 2007Lecture 5 - Verilog Simulation39 Verilog Tasks (cont'd)  Task example: task ReverseByte; input [7:0] a; output [7:0] ra; integer j; begin for (j = 7; j >=0; j=j-1) ra[j] = a[7-j]; end endtask // Adapted from "Verilog HDL Synthesis: A Practical // Primer", by J. Bhasker

40. ECE 491 Fall 2007Lecture 5 - Verilog Simulation40 System Tasks and Functions  Tasks and functions defined for simulator control  All named starting with " $ " (e.g., $monitor )  Standard - same for every simulator (almost)  See Verilog Quick Reference Card, Section 8 for full list of system tasks  Example system task: $display $display("format-string", expr1, …, exprn); format-string - regular ASCII mixed with formatting characters %d - decimal, %b - binary, %h - hex, %t - time, etc. other arguments: any expression, including wire s and reg s $display("Error at time %t: value is %h, expected %h", $time, actual_value, expected_value);

41. ECE 491 Fall 2007Lecture 5 - Verilog Simulation41 Some useful System Tasks  $time - return current simulation time  $monitor - print message when values change $monitor("cs=%b, ns=%b", cs, ns)  Simulation control tasks  $stop - interrupt simulation  $finish - terminate simulation  Extensive file I/O also available

42. ECE 491 Fall 2007Lecture 5 - Verilog Simulation42 Verilog Stuff we Won’t Talk About  Parallel Blocks - fork / join  Procedural continuous assignment  assign / deassign as procedural statements  Not synthesizeable  User-Defined Primitives (UDPs) - low-level gate models  Programming Language Interface (PLI) - for linking to programming code in C/C++

43. ECE 491 Fall 2007Lecture 5 - Verilog Simulation43 Verilog - Recent Developments  Verilog 2001(IEEE Standard) - Adds several new features  Cleaner module specifications  Lots of “syntatic sugar” - features that make language “nicer” to use  System Verilog  Meant to allow verification and HW/SW codesign  Integrates many features of C: C primitive types Structures Enumerated Types Recursion

44. ECE 491 Fall 2007Lecture 5 - Verilog Simulation44 Verilog 2001 Port Declarations  Combines port list and declarations module counter( input clk, input enb, output reg [3:0] Q, output carry); always @(posedge clk) if (enb) Q <= Q + 1; endmodule

45. ECE 491 Fall 2007Lecture 5 - Verilog Simulation45 HDLs - What Else is Out There?  VHDL  More general; more verbose  Continued extension - VHDL 2001 is current standard  SystemC  C++ class library of synthesizeable constructs  Meant for large system hardware/software codesign  Reference: www.systemc.org www.systemc.org  Verification Languages  e - Cadence  Vera - Synopsys Focus on constrained random verification

46. ECE 491 Fall 2007Lecture 5 - Verilog Simulation46 Coming Up  Verification and Testbenches  Serial Data Communication